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Searched refs:smc_state_table (Results 1 – 21 of 21) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Dtonga_smumgr.c520 smu_data->smc_state_table.LinkLevelCount = in tonga_populate_smc_link_level()
720 smu_data->smc_state_table.GraphicsDpmLevelCount = in tonga_populate_all_graphic_levels()
1092 smu_data->smc_state_table.MemoryLevel; in tonga_populate_all_memory_levels()
1104 &(smu_data->smc_state_table.MemoryLevel[i])); in tonga_populate_all_memory_levels()
1540 smu_data->smc_state_table.MemoryBootLevel = 0; in tonga_populate_smc_boot_level()
2224 memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table)); in tonga_init_smc_table()
2671 smu_data->smc_state_table.UvdBootLevel = 0; in tonga_update_uvd_smc_table()
2673 smu_data->smc_state_table.UvdBootLevel = in tonga_update_uvd_smc_table()
2706 smu_data->smc_state_table.VceBootLevel = in tonga_update_vce_smc_table()
3143 smu_data->smc_state_table.GraphicsLevel; in tonga_update_dpm_settings()
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H A Dfiji_smumgr.c859 smu_data->smc_state_table.LinkLevelCount = in fiji_populate_smc_link_level()
1029 smu_data->smc_state_table.GraphicsLevel; in fiji_populate_all_graphic_levels()
1055 smu_data->smc_state_table.GraphicsDpmLevelCount = in fiji_populate_all_graphic_levels()
1244 smu_data->smc_state_table.MemoryLevel; in fiji_populate_all_memory_levels()
1269 smu_data->smc_state_table.MemoryDpmLevelCount = in fiji_populate_all_memory_levels()
2382 smu_data->smc_state_table.UvdBootLevel = 0; in fiji_update_uvd_smc_table()
2384 smu_data->smc_state_table.UvdBootLevel = in fiji_update_uvd_smc_table()
2416 smu_data->smc_state_table.VceBootLevel = in fiji_update_vce_smc_table()
2419 smu_data->smc_state_table.VceBootLevel = 0; in fiji_update_vce_smc_table()
2564 smu_data->smc_state_table.GraphicsLevel; in fiji_update_dpm_settings()
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H A Dpolaris10_smumgr.c786 smu_data->smc_state_table.LinkLevelCount = in polaris10_populate_smc_link_level()
991 smu_data->smc_state_table.GraphicsLevel; in polaris10_populate_all_graphic_levels()
1017 smu_data->smc_state_table.GraphicsDpmLevelCount = in polaris10_populate_all_graphic_levels()
1134 smu_data->smc_state_table.MemoryLevel; in polaris10_populate_all_memory_levels()
1160 smu_data->smc_state_table.MemoryDpmLevelCount = in polaris10_populate_all_memory_levels()
2129 smu_data->smc_state_table.UvdBootLevel = 0; in polaris10_update_uvd_smc_table()
2131 smu_data->smc_state_table.UvdBootLevel = in polaris10_update_uvd_smc_table()
2163 smu_data->smc_state_table.VceBootLevel = in polaris10_update_vce_smc_table()
2166 smu_data->smc_state_table.VceBootLevel = 0; in polaris10_update_vce_smc_table()
2411 smu_data->smc_state_table.GraphicsLevel; in polaris10_update_dpm_settings()
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H A Dci_smumgr.c481 smu_data->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
1013 smu_data->smc_state_table.LinkLevelCount = in ci_populate_smc_link_level()
1317 &(smu_data->smc_state_table.MemoryLevel[i])); in ci_populate_all_memory_levels()
1328 smu_data->smc_state_table.MemoryLevel[1].MinVddci = in ci_populate_all_memory_levels()
1330 smu_data->smc_state_table.MemoryLevel[1].MinMvdd = in ci_populate_all_memory_levels()
1698 smu_data->smc_state_table.GraphicsBootLevel = 0; in ci_populate_smc_boot_level()
1708 smu_data->smc_state_table.MemoryBootLevel = 0; in ci_populate_smc_boot_level()
1949 memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table)); in ci_init_smc_table()
2764 smu_data->smc_state_table.GraphicsLevel; in ci_update_dpm_settings()
2771 smu_data->smc_state_table.MemoryLevel; in ci_update_dpm_settings()
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H A Dvegam_smumgr.c339 smu_data->smc_state_table.UvdBootLevel = 0; in vegam_update_uvd_smc_table()
341 smu_data->smc_state_table.UvdBootLevel = in vegam_update_uvd_smc_table()
373 smu_data->smc_state_table.VceBootLevel = in vegam_update_vce_smc_table()
376 smu_data->smc_state_table.VceBootLevel = 0; in vegam_update_vce_smc_table()
590 smu_data->smc_state_table.LinkLevelCount = in vegam_populate_smc_link_level()
879 smu_data->smc_state_table.GraphicsLevel; in vegam_populate_all_graphic_levels()
892 &(smu_data->smc_state_table.GraphicsLevel[i])); in vegam_populate_all_graphic_levels()
908 smu_data->smc_state_table.GraphicsDpmLevelCount = in vegam_populate_all_graphic_levels()
1045 smu_data->smc_state_table.MemoryLevel; in vegam_populate_all_memory_levels()
1065 smu_data->smc_state_table.MemoryDpmLevelCount = in vegam_populate_all_memory_levels()
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H A Diceland_smumgr.c787 smu_data->smc_state_table.LinkLevelCount = in iceland_populate_smc_link_level()
983 &(smu_data->smc_state_table.GraphicsLevel[i])); in iceland_populate_all_graphic_levels()
1000 smu_data->smc_state_table.GraphicsDpmLevelCount = in iceland_populate_all_graphic_levels()
1364 &(smu_data->smc_state_table.MemoryLevel[i])); in iceland_populate_all_memory_levels()
1378 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; in iceland_populate_all_memory_levels()
1661 smu_data->smc_state_table.GraphicsBootLevel = 0; in iceland_populate_smc_boot_level()
1668 (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel)); in iceland_populate_smc_boot_level()
1671 smu_data->smc_state_table.MemoryBootLevel = 0; in iceland_populate_smc_boot_level()
1830 smu_data->smc_state_table.GraphicsBootLevel = level; in iceland_populate_smc_initial_state()
1840 smu_data->smc_state_table.MemoryBootLevel = level; in iceland_populate_smc_initial_state()
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H A Dfiji_smumgr.h42 struct SMU73_Discrete_DpmTable smc_state_table; member
H A Dpolaris10_smumgr.h57 SMU74_Discrete_DpmTable smc_state_table; member
H A Diceland_smumgr.h62 struct SMU71_Discrete_DpmTable smc_state_table; member
H A Dvegam_smumgr.h66 SMU75_Discrete_DpmTable smc_state_table; member
H A Dci_smumgr.h68 struct SMU7_Discrete_DpmTable smc_state_table; member
H A Dtonga_smumgr.h66 struct SMU72_Discrete_DpmTable smc_state_table; member
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dvega10_hwmgr.c3504 data->smc_state_table.gfx_boot_level = in vega10_generate_dpm_level_enable_mask()
3506 data->smc_state_table.gfx_max_level = in vega10_generate_dpm_level_enable_mask()
3510 data->smc_state_table.mem_max_level = in vega10_generate_dpm_level_enable_mask()
3519 for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++) in vega10_generate_dpm_level_enable_mask()
3523 for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++) in vega10_generate_dpm_level_enable_mask()
3860 data->smc_state_table.gfx_max_level = in vega10_force_dpm_highest()
3863 data->smc_state_table.mem_max_level = in vega10_force_dpm_highest()
3882 data->smc_state_table.gfx_max_level = in vega10_force_dpm_lowest()
3885 data->smc_state_table.mem_max_level = in vega10_force_dpm_lowest()
3906 data->smc_state_table.gfx_max_level = in vega10_unforce_dpm_levels()
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H A Dvega10_thermal.c509 PPTable_t *table = &(data->smc_state_table.pp_table); in vega10_thermal_setup_fan_table()
553 (uint8_t *)(&(data->smc_state_table.pp_table)), in vega10_thermal_setup_fan_table()
H A Dvega12_thermal.c261 PPTable_t *table = &(data->smc_state_table.pp_table); in vega12_thermal_setup_fan_table()
H A Dvega10_hwmgr.h380 struct vega10_smc_state_table smc_state_table; member
H A Dvega12_hwmgr.h393 struct vega12_smc_state_table smc_state_table; member
H A Dvega12_hwmgr.c723 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega12_init_smc_table()
1780 Watermarks_t *table = &(data->smc_state_table.water_marks_table); in vega12_set_watermarks_for_clocks_ranges()
2104 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega12_display_configuration_changed_task()
H A Dvega10_powertune.c1294 PPTable_t *table = &(data->smc_state_table.pp_table); in vega10_initialize_power_tune_defaults()
/dragonfly/sys/dev/drm/radeon/
H A Dci_dpm.c2630 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2638 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
3327 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3375 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3384 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3385 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3669 (u32 *)&pi->smc_state_table.MemoryBootLevel); in ci_init_smc_table()
4116 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4118 pi->smc_state_table.UvdBootLevel = in ci_update_uvd_dpm()
4187 pi->smc_state_table.AcpBootLevel = 0;
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H A Dci_dpm.h223 SMU7_Discrete_DpmTable smc_state_table; member