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Searched refs:tg_inst (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_hwseq.c168 unsigned int tg_inst) in dce_crtc_switch_to_clk_src() argument
171 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
177 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
181 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
187 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
191 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst])) in dce_crtc_switch_to_clk_src()
192 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
196 clk_src->id, tg_inst); in dce_crtc_switch_to_clk_src()
H A Ddce_stream_encoder.c1552 int tg_inst, bool enable) in setup_stereo_sync() argument
1555 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in setup_stereo_sync()
H A Ddce_hwseq.h542 unsigned int tg_inst);
/dragonfly/sys/dev/drm/amd/display/dc/inc/hw/
H A Dstream_encoder.h154 int tg_inst,
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.c1412 int tg_inst, bool enable) in enc1_setup_stereo_sync() argument
1415 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in enc1_setup_stereo_sync()
H A Ddcn10_stream_encoder.h494 int tg_inst, bool enable);