| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 3717 { ISD::FSQRT, MVT::f32, { 7, 15, 1, 1 } }, // vsqrtss in getIntrinsicInstrCost()
3811 { ISD::FSQRT, MVT::f32, { 19, 20, 1, 1 } }, // sqrtss in getIntrinsicInstrCost()
3812 { ISD::FSQRT, MVT::v4f32, { 37, 41, 1, 5 } }, // sqrtps in getIntrinsicInstrCost()
3813 { ISD::FSQRT, MVT::f64, { 34, 35, 1, 1 } }, // sqrtsd in getIntrinsicInstrCost()
3814 { ISD::FSQRT, MVT::v2f64, { 67, 71, 1, 5 } }, // sqrtpd in getIntrinsicInstrCost()
3820 { ISD::FSQRT, MVT::f32, { 20, 20, 1, 1 } }, // sqrtss in getIntrinsicInstrCost()
3821 { ISD::FSQRT, MVT::v4f32, { 40, 41, 1, 5 } }, // sqrtps in getIntrinsicInstrCost()
3822 { ISD::FSQRT, MVT::f64, { 35, 35, 1, 1 } }, // sqrtsd in getIntrinsicInstrCost()
3823 { ISD::FSQRT, MVT::v2f64, { 70, 71, 1, 5 } }, // sqrtpd in getIntrinsicInstrCost()
4119 ISD = ISD::FSQRT; in getIntrinsicInstrCost()
[all …]
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| H A D | X86IntrinsicsInfo.h | 928 X86_INTRINSIC_DATA(avx512_sqrt_pd_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
929 X86_INTRINSIC_DATA(avx512_sqrt_ps_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
1208 X86_INTRINSIC_DATA(avx512fp16_sqrt_ph_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
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| H A D | X86.td | 613 // TuningFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
615 // vector FSQRT has higher throughput than the corresponding NR code.
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| /freebsd/contrib/one-true-awk/ |
| H A D | awk.h | 144 #define FSQRT 2 macro
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| H A D | lex.c | 88 { "sqrt", FSQRT, BLTIN },
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 97 DAG_FUNCTION(sqrt, 1, 1, experimental_constrained_sqrt, FSQRT)
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| H A D | VPIntrinsics.def | 346 VP_PROPERTY_FUNCTIONAL_SDOPC(FSQRT)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 930 FSQRT, enumerator
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| H A D | BasicTTIImpl.h | 531 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
1878 ISD = ISD::FSQRT; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedCyclone.td | 553 // FDIV,FSQRT
555 // TODO: Specialize FSQRT for longer latency.
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCScheduleP7.td | 309 def : InstRW<[P7_ScalarFPU_44C, P7_DISP_FP], (instrs FSQRT, FSQRT_rec)>;
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| H A D | PPCScheduleP8.td | 163 def : InstRW<[P8_FP_Scal_43C, P8_ISSUE_VSX], (instrs FSQRT, FSQRT_rec, XSSQRTDP)>;
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| H A D | PPCISelLowering.h | 93 FSQRT, enumerator
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| H A D | P10InstrResources.td | 71 FSQRT,
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| H A D | P9InstrResources.td | 1153 FSQRT
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrFPU.td | 122 defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
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| H A D | MipsSEISelLowering.cpp | 147 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in MipsSETargetLowering()
387 setOperationAction(ISD::FSQRT, Ty, Legal); in addMSAFloatType()
1908 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsInstrFPU.td | 543 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 201 case ISD::FSQRT: return "fsqrt"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 132 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
1353 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
2418 case ISD::FSQRT: in PromoteFloatResult()
2827 case ISD::FSQRT: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 392 case ISD::FSQRT: in LegalizeOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1907 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1932 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1984 setOperationAction(ISD::FSQRT, MVT::f32, Promote); in SparcTargetLowering()
3288 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfoF1.td | 121 defm FSQRT : FT_XZ<0b011010, "fsqrt", UnOpFrag<(fsqrt node:$Src)>>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 210 ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FSQRT, ISD::FCBRT, in SITargetLowering()
273 setOperationAction(ISD::FSQRT, {MVT::f32, MVT::f64}, Custom); in SITargetLowering()
477 setOperationAction(ISD::FSQRT, MVT::f16, Custom); in SITargetLowering()
5534 case ISD::FSQRT: { in LowerOperation()
6051 case ISD::FSQRT: { in ReplaceNodeResults()
12317 if ((VT == MVT::f16 && N0.getOpcode() == ISD::FSQRT) && in performRcpCombine()
12358 case ISD::FSQRT: in isCanonicalized()
14101 if (RHS.getOpcode() == ISD::FSQRT) { in performFDivCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1589 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1634 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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