/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMRegisterInfo.td | 259 // GPRs without the PC. Some ARM instructions do not allow the PC in 271 // GPRs without the PC but with APSR. Some instructions allow accessing the 282 // GPRs without the SP register. Used for BXAUT and AUTG 292 // GPRs without the PC and SP registers but with APSR. Used by CLRM instruction. 339 // GPRs without the PC and SP but with APSR_NZCV.Some instructions allow 529 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP. 530 // These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs. 538 // Register class representing a pair of even-odd GPRs. 543 // Register class representing a pair of even-odd GPRs, except (R12, SP).
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H A D | ARMCallingConv.td | 36 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack 133 // i64/f64 is passed in even pairs of GPRs
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/freebsd/contrib/llvm-project/libunwind/src/ |
H A D | Registers.hpp | 97 struct GPRs { struct in libunwind::Registers_x86 116 GPRs _registers; 315 struct GPRs { struct in libunwind::Registers_x86_64 341 GPRs _registers; 1847 struct GPRs { struct in libunwind::Registers_arm64 1856 GPRs _registers; 1868 static_assert(sizeof(GPRs) == 0x110, in Registers_arm64() 1871 static_cast<const uint8_t *>(registers) + sizeof(GPRs), in Registers_arm64() 2159 struct GPRs { struct in libunwind::Registers_arm 2185 GPRs _registers;
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZCallingConv.td | 209 // Even though 3 GPRs, 4 FPRs, and 8 VRs may be used, 212 // GPRs 1-3. FP values and vector-type arguments are instead passed in FPRs 225 // Promote f32 to f64 and bitcast to i64, if it needs to be passed in GPRs.
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H A D | SystemZFrameLowering.cpp | 1297 auto &GPRs = SystemZ::XPLINK64ArgGPRs; in emitPrologue() local 1302 unsigned Reg = GPRs[I]; in emitPrologue()
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H A D | SystemZInstrVector.td | 1781 // Moving 32-bit values between GPRs and FPRs can be done using VLVGF
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCGenRegisterBankInfo.def | 104 // GPRs, FPRs and vectors. It currently only handles bitcasting to
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H A D | PPCCallingConv.td | 117 // vectors within registers, as well as it handles the shadowing of GPRs 146 // Handle support for vector types, and shadow GPRs as necessary. 284 // in a GPR (or in the parameter list area if all GPRs are allocated) from the
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H A D | PPCISelLowering.cpp | 6877 ArrayRef<MCPhysReg> GPRs = IsPPC64 ? GPR_64 : GPR_32; in CC_AIX() local 6879 unsigned NextRegIndex = State.getFirstUnallocated(GPRs); in CC_AIX() 6882 while (NextRegIndex != GPRs.size() && in CC_AIX() 6883 !isGPRShadowAligned(GPRs[NextRegIndex], VecAlign)) { in CC_AIX() 6885 unsigned Reg = State.AllocateReg(GPRs); in CC_AIX() 6889 NextRegIndex = State.getFirstUnallocated(GPRs); in CC_AIX() 6901 State.AllocateReg(GPRs); in CC_AIX() 6912 if (NextRegIndex == GPRs.size()) { in CC_AIX() 6921 if (GPRs[NextRegIndex] == PPC::R9) { in CC_AIX() 6944 const unsigned Reg = State.AllocateReg(GPRs); in CC_AIX()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfoD.td | 485 // Moves two GPRs to an FPR. 491 // Moves an FPR to two GPRs. 530 // Moves two GPRs to an FPR. 536 // Moves an FPR to two GPRs.
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H A D | RISCVFeatures.td | 1002 "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;
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/freebsd/sys/contrib/device-tree/Bindings/powerpc/opal/ |
H A D | power-mgt.txt | 46 0x00001000 /* Restore GPRs like nap */
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/freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
H A D | arm_cde.td | 60 // CX* instructions operating on GPRs
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86CallingConv.td | 669 // The first 4 MMX vector arguments are passed in GPRs. 673 // GPRs or on the stack. 1140 // GPRs are preserved. 1150 // All GPRs - except r11 and return registers.
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H A D | X86InstrOperands.td | 129 // GPRs available for tailcall.
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H A D | X86RegisterInfo.td | 580 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since 590 // GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ValueTypes.td | 283 def i64x8 : ValueType<512, 195>; // 8 Consecutive GPRs (AArch64)
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64CallingConvention.td | 254 // The first 4 MMX vector arguments are passed in GPRs.
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H A D | AArch64RegisterInfo.td | 757 // Armv8.7a accelerator extension register operands: 8 consecutive GPRs
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H A D | AArch64InstrInfo.td | 9216 // Custom DAG nodes and isel rules to make a 64-byte block out of eight GPRs,
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | Mips16InstrInfo.td | 693 // To compare the contents of two GPRs.
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAG.td | 1948 // their GPRs).
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