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Searched refs:GPRs (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td259 // GPRs without the PC. Some ARM instructions do not allow the PC in
271 // GPRs without the PC but with APSR. Some instructions allow accessing the
282 // GPRs without the SP register. Used for BXAUT and AUTG
292 // GPRs without the PC and SP registers but with APSR. Used by CLRM instruction.
339 // GPRs without the PC and SP but with APSR_NZCV.Some instructions allow
529 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
530 // These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.
538 // Register class representing a pair of even-odd GPRs.
543 // Register class representing a pair of even-odd GPRs, except (R12, SP).
H A DARMCallingConv.td36 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
133 // i64/f64 is passed in even pairs of GPRs
/freebsd/contrib/llvm-project/libunwind/src/
H A DRegisters.hpp97 struct GPRs { struct in libunwind::Registers_x86
116 GPRs _registers;
315 struct GPRs { struct in libunwind::Registers_x86_64
341 GPRs _registers;
1847 struct GPRs { struct in libunwind::Registers_arm64
1856 GPRs _registers;
1868 static_assert(sizeof(GPRs) == 0x110, in Registers_arm64()
1871 static_cast<const uint8_t *>(registers) + sizeof(GPRs), in Registers_arm64()
2159 struct GPRs { struct in libunwind::Registers_arm
2185 GPRs _registers;
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td209 // Even though 3 GPRs, 4 FPRs, and 8 VRs may be used,
212 // GPRs 1-3. FP values and vector-type arguments are instead passed in FPRs
225 // Promote f32 to f64 and bitcast to i64, if it needs to be passed in GPRs.
H A DSystemZFrameLowering.cpp1297 auto &GPRs = SystemZ::XPLINK64ArgGPRs; in emitPrologue() local
1302 unsigned Reg = GPRs[I]; in emitPrologue()
H A DSystemZInstrVector.td1781 // Moving 32-bit values between GPRs and FPRs can be done using VLVGF
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCGenRegisterBankInfo.def104 // GPRs, FPRs and vectors. It currently only handles bitcasting to
H A DPPCCallingConv.td117 // vectors within registers, as well as it handles the shadowing of GPRs
146 // Handle support for vector types, and shadow GPRs as necessary.
284 // in a GPR (or in the parameter list area if all GPRs are allocated) from the
H A DPPCISelLowering.cpp6877 ArrayRef<MCPhysReg> GPRs = IsPPC64 ? GPR_64 : GPR_32; in CC_AIX() local
6879 unsigned NextRegIndex = State.getFirstUnallocated(GPRs); in CC_AIX()
6882 while (NextRegIndex != GPRs.size() && in CC_AIX()
6883 !isGPRShadowAligned(GPRs[NextRegIndex], VecAlign)) { in CC_AIX()
6885 unsigned Reg = State.AllocateReg(GPRs); in CC_AIX()
6889 NextRegIndex = State.getFirstUnallocated(GPRs); in CC_AIX()
6901 State.AllocateReg(GPRs); in CC_AIX()
6912 if (NextRegIndex == GPRs.size()) { in CC_AIX()
6921 if (GPRs[NextRegIndex] == PPC::R9) { in CC_AIX()
6944 const unsigned Reg = State.AllocateReg(GPRs); in CC_AIX()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td485 // Moves two GPRs to an FPR.
491 // Moves an FPR to two GPRs.
530 // Moves two GPRs to an FPR.
536 // Moves an FPR to two GPRs.
H A DRISCVFeatures.td1002 "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;
/freebsd/sys/contrib/device-tree/Bindings/powerpc/opal/
H A Dpower-mgt.txt46 0x00001000 /* Restore GPRs like nap */
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_cde.td60 // CX* instructions operating on GPRs
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td669 // The first 4 MMX vector arguments are passed in GPRs.
673 // GPRs or on the stack.
1140 // GPRs are preserved.
1150 // All GPRs - except r11 and return registers.
H A DX86InstrOperands.td129 // GPRs available for tailcall.
H A DX86RegisterInfo.td580 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
590 // GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.td283 def i64x8 : ValueType<512, 195>; // 8 Consecutive GPRs (AArch64)
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td254 // The first 4 MMX vector arguments are passed in GPRs.
H A DAArch64RegisterInfo.td757 // Armv8.7a accelerator extension register operands: 8 consecutive GPRs
H A DAArch64InstrInfo.td9216 // Custom DAG nodes and isel rules to make a 64-byte block out of eight GPRs,
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.td693 // To compare the contents of two GPRs.
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td1948 // their GPRs).