/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_gfx_v7_0.c | 2281 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v7_0_ring_emit_ib_gfx() 2283 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v7_0_ring_emit_ib_gfx() 2379 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); in gfx_v7_0_ring_test_ib() 2552 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v7_0_cp_gfx_start() 3295 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_wreg() 4105 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch() 4113 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch() 4121 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch() 4129 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch() 5010 .nop = PACKET3(PACKET3_NOP, 0x3FFF), [all …]
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H A D | amdgpu_gfx_v6_0.c | 1834 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush() 1848 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence() 1882 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v6_0_ring_emit_ib() 1884 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v6_0_ring_emit_ib() 1926 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in gfx_v6_0_ring_test_ib() 2049 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v6_0_cp_gfx_start() 2070 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v6_0_cp_gfx_start() 2081 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v6_0_cp_gfx_start() 2317 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v6_0_ring_emit_pipeline_sync() 2344 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v6_0_ring_emit_vm_flush() [all …]
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H A D | amdgpu_gfx_v8_0.c | 903 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v8_0_ring_test_ib() 1582 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds() 1608 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds() 1634 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds() 4201 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v8_0_cp_gfx_start() 4223 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v8_0_cp_gfx_start() 6096 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v8_0_ring_emit_ib_gfx() 6098 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v8_0_ring_emit_ib_gfx() 6909 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6954 .nop = PACKET3(PACKET3_NOP, 0x3FFF), [all …]
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H A D | amdgpu_gfx_v9_0.c | 948 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_write_data_to_reg() 1038 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v9_0_ring_test_ib() 3144 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v9_0_cp_gfx_start() 3160 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v9_0_cp_gfx_start() 4172 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in gfx_v9_0_do_edc_gds_workarounds() 4919 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v9_0_ring_emit_ib_gfx() 4921 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v9_0_ring_emit_ib_gfx() 5282 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); in gfx_v9_0_ring_emit_init_cond_exec() 6445 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6496 .nop = PACKET3(PACKET3_NOP, 0x3FFF), [all …]
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H A D | amdgpu_gfx_v10_0.c | 428 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v10_0_write_data_to_reg() 529 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); in gfx_v10_0_ring_test_ib() 2690 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v10_0_cp_gfx_start() 2712 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v10_0_cp_gfx_start() 4417 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); in gfx_v10_0_ring_emit_ib_gfx() 4419 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v10_0_ring_emit_ib_gfx() 4613 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); in gfx_v10_0_ring_emit_init_cond_exec() 4751 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); in gfx_v10_0_ring_emit_rreg() 5154 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5206 .nop = PACKET3(PACKET3_NOP, 0x3FFF), [all …]
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H A D | si_enums.h | 171 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro 174 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | nvd.h | 50 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 54 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | soc15d.h | 52 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 56 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | vid.h | 109 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 113 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | cikd.h | 227 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 231 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | sid.h | 1660 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro 1664 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | amdgpu_amdkfd_gfx_v9.c | 359 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_gfx_v9_hiq_mqd_load()
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H A D | amdgpu_amdkfd_gfx_v10.c | 371 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_hiq_mqd_load()
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/netbsd/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_ni.c | 1418 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit() 1424 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit() 1440 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in cayman_ring_ib_execute() 1445 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_ring_ib_execute() 1461 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_ring_ib_execute() 1567 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in cayman_cp_start() 1585 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start() 1591 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start() 1595 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start() 2715 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cayman_vm_flush() [all …]
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H A D | radeon_cik.c | 3707 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma() 3757 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in cik_ring_ib_execute() 3775 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in cik_ring_ib_execute() 3816 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); in cik_ib_test() 4017 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in cik_cp_gfx_start() 5710 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush() 5724 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush() 5731 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); in cik_vm_flush() 5742 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush() 8471 nop = PACKET3(PACKET3_NOP, 0x3FFF); in cik_startup() [all …]
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H A D | radeon_si.c | 3391 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_fence_ring_emit() 3422 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in si_ring_ib_execute() 3433 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_ring_ib_execute() 3440 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in si_ring_ib_execute() 3588 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in si_cp_start() 3613 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in si_cp_start() 5087 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush() 5102 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush() 5110 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush() 5118 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in si_vm_flush() [all …]
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H A D | radeon_r600.c | 2729 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start() 2874 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test() 2912 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit() 2926 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit() 2931 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in r600_fence_ring_emit() 2969 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in r600_semaphore_ring_emit() 2976 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in r600_semaphore_ring_emit() 3023 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_copy_cpdma() 3034 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); in r600_copy_cpdma() 3415 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in r600_ring_ib_execute() [all …]
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H A D | r300d.h | 66 #define PACKET3(op, n) (CP_PACKET3 | \ macro
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H A D | radeon_evergreen.c | 2943 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in evergreen_ring_ib_execute() 2948 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in evergreen_ring_ib_execute() 2954 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in evergreen_ring_ib_execute() 2961 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in evergreen_ring_ib_execute() 3015 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in evergreen_cp_start() 3034 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start() 3040 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start() 3044 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in evergreen_cp_start()
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H A D | sid.h | 1597 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro 1601 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | cikd.h | 1693 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 1697 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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H A D | rv515d.h | 206 #define PACKET3(op, n) (CP_PACKET3 | \ macro
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H A D | rv770d.h | 990 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
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H A D | nid.h | 1159 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
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H A D | r100d.h | 65 #define PACKET3(op, n) (CP_PACKET3 | \ macro
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