Searched refs:PACKET3_SET_BASE (Results 1 – 18 of 18) sorted by relevance
| /netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | si_enums.h | 176 #define PACKET3_SET_BASE 0x11 macro
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| H A D | nvd.h | 58 #define PACKET3_SET_BASE 0x11 macro
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| H A D | soc15d.h | 83 #define PACKET3_SET_BASE 0x11 macro
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| H A D | vid.h | 117 #define PACKET3_SET_BASE 0x11 macro
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| H A D | cikd.h | 235 #define PACKET3_SET_BASE 0x11 macro
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| H A D | sid.h | 1668 #define PACKET3_SET_BASE 0x11 macro
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| H A D | amdgpu_gfx_v6_0.c | 2049 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v6_0_cp_gfx_start()
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| H A D | amdgpu_gfx_v7_0.c | 2552 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v7_0_cp_gfx_start()
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| H A D | amdgpu_gfx_v10_0.c | 2712 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v10_0_cp_gfx_start()
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| H A D | amdgpu_gfx_v9_0.c | 3160 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v9_0_cp_gfx_start()
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| H A D | amdgpu_gfx_v8_0.c | 4223 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v8_0_cp_gfx_start()
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| /netbsd/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | nid.h | 1165 #define PACKET3_SET_BASE 0x11 macro
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| H A D | sid.h | 1605 #define PACKET3_SET_BASE 0x11 macro
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| H A D | cikd.h | 1701 #define PACKET3_SET_BASE 0x11 macro
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| H A D | radeon_si.c | 3588 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in si_cp_start()
4469 case PACKET3_SET_BASE: in si_vm_packet3_ce_check()
4547 case PACKET3_SET_BASE: in si_vm_packet3_gfx_check()
4665 case PACKET3_SET_BASE: in si_vm_packet3_compute_check()
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| H A D | radeon_evergreen_cs.c | 2026 case PACKET3_SET_BASE: in evergreen_packet3_check()
3388 case PACKET3_SET_BASE: in evergreen_vm_packet3_check()
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| H A D | evergreend.h | 1551 #define PACKET3_SET_BASE 0x11 macro
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| H A D | radeon_cik.c | 4017 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in cik_cp_gfx_start()
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