Searched refs:WRITE_DATA_DST_SEL (Results 1 – 15 of 15) sorted by relevance
155 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
91 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
112 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
146 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
264 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
904 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()5183 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5191 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5199 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5207 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()6375 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()6384 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()7196 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_ce_meta()7229 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_de_meta()
3297 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_wreg()4107 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4115 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4123 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4131 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
950 WRITE_DATA_DST_SEL(0) | in gfx_v9_0_write_data_to_reg()1039 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()5176 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5185 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5209 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_ce_meta()5231 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_de_meta()
430 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()4552 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()4561 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()4688 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_ce_meta()4722 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_de_meta()
1702 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
2373 WRITE_DATA_DST_SEL(0))); in gfx_v6_0_ring_emit_wreg()
1639 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3769 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()5712 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5726 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5733 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5744 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5755 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
1730 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
5089 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5104 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5112 WRITE_DATA_DST_SEL(0))); in si_vm_flush()