| /openbsd/sys/dev/pci/drm/radeon/ |
| H A D | rv740d.h | 66 #define MCLK_PWRMGT_CNTL 0x648 macro
|
| H A D | rv6xxd.h | 47 #define MCLK_PWRMGT_CNTL 0x624 macro
|
| H A D | rv740_dpm.c | 311 RREG32(MCLK_PWRMGT_CNTL); in rv740_read_clock_registers()
|
| H A D | r600_dpm.c | 314 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); in r600_enable_mclk_control()
316 WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); in r600_enable_mclk_control()
|
| H A D | rv770d.h | 171 #define MCLK_PWRMGT_CNTL 0x648 macro
|
| H A D | rv770_dpm.c | 185 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); in rv770_start_dpm()
203 WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); in rv770_stop_dpm()
1541 RREG32(MCLK_PWRMGT_CNTL); in rv770_read_clock_registers()
|
| H A D | nid.h | 613 #define MCLK_PWRMGT_CNTL 0x648 macro
|
| H A D | rv6xx_dpm.c | 991 WREG32_P(MCLK_PWRMGT_CNTL, USE_DISPLAY_GAP, ~USE_DISPLAY_GAP); in rv6xx_enable_display_gap()
993 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP); in rv6xx_enable_display_gap()
|
| H A D | cypress_dpm.c | 256 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); in cypress_enable_mclk_control()
258 WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); in cypress_enable_mclk_control()
|
| H A D | sid.h | 596 #define MCLK_PWRMGT_CNTL 0x2ba0 macro
|
| H A D | cikd.h | 721 #define MCLK_PWRMGT_CNTL 0x2ba0 macro
|
| H A D | evergreend.h | 151 #define MCLK_PWRMGT_CNTL 0x648 macro
|
| H A D | r600d.h | 1325 #define MCLK_PWRMGT_CNTL 0x624 macro
|
| H A D | ni_dpm.c | 1193 ni_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in ni_read_clock_registers()
|
| H A D | si_dpm.c | 3559 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in si_read_clock_registers()
|
| H A D | ci_dpm.c | 1850 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in ci_read_clock_registers()
|
| /openbsd/sys/dev/pci/drm/amd/pm/powerplay/smumgr/ |
| H A D | iceland_smumgr.c | 1147 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed); in iceland_calculate_mclk_params()
1149 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn); in iceland_calculate_mclk_params()
1151 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn); in iceland_calculate_mclk_params()
1512 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); in iceland_populate_smc_acpi_level()
1514 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1); in iceland_populate_smc_acpi_level()
1518 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0); in iceland_populate_smc_acpi_level()
1520 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0); in iceland_populate_smc_acpi_level()
|
| H A D | ci_smumgr.c | 1098 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed); in ci_calculate_mclk_params()
1100 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn); in ci_calculate_mclk_params()
1102 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn); in ci_calculate_mclk_params()
1466 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); in ci_populate_smc_acpi_level()
1468 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1); in ci_populate_smc_acpi_level()
1472 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0); in ci_populate_smc_acpi_level()
1474 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0); in ci_populate_smc_acpi_level()
|
| H A D | tonga_smumgr.c | 899 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed); in tonga_calculate_mclk_params()
901 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn); in tonga_calculate_mclk_params()
903 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn); in tonga_calculate_mclk_params()
1254 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); in tonga_populate_smc_acpi_level()
1256 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1); in tonga_populate_smc_acpi_level()
1260 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0); in tonga_populate_smc_acpi_level()
1262 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0); in tonga_populate_smc_acpi_level()
|
| /openbsd/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | sid.h | 597 #define MCLK_PWRMGT_CNTL 0xAE8 macro
|
| /openbsd/sys/dev/pci/drm/amd/pm/legacy-dpm/ |
| H A D | amdgpu_si_dpm.c | 4033 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in si_read_clock_registers()
|