Home
last modified time | relevance | path

Searched refs:mmCP_HQD_DEQUEUE_REQUEST (Results 1 – 18 of 18) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v7.c426 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
441 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); in kgd_hqd_destroy()
H A Damdgpu_amdkfd_gfx_v8.c461 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
476 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); in kgd_hqd_destroy()
H A Damdgpu_amdkfd_gfx_v10.c591 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
607 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type); in kgd_hqd_destroy()
H A Damdgpu_amdkfd_gfx_v10_3.c530 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type); in hqd_destroy_v10_3()
H A Damdgpu_amdkfd_gfx_v9.c559 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST), type); in kgd_gfx_v9_hqd_destroy()
H A Dgfx_v9_0.c3400 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v9_0_kiq_init_register()
3406 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v9_0_kiq_init_register()
3498 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v9_0_kiq_fini_register()
3513 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v9_0_kiq_fini_register()
H A Dgfx_v7_0.c2834 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v7_0_mqd_deactivate()
2844 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); in gfx_v7_0_mqd_deactivate()
H A Dgfx_v10_0.c6629 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v10_0_kiq_init_register()
6635 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, in gfx_v10_0_kiq_init_register()
H A Dgfx_v8_0.c4391 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); in gfx_v8_0_deactivate_hqd()
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h591 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
H A Dgfx_7_2_d.h604 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
H A Dgfx_8_0_d.h654 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
H A Dgfx_8_1_d.h654 #define mmCP_HQD_DEQUEUE_REQUEST 0x325d macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2865 #define mmCP_HQD_DEQUEUE_REQUEST macro
H A Dgc_9_2_1_offset.h3049 #define mmCP_HQD_DEQUEUE_REQUEST macro
H A Dgc_9_1_offset.h3093 #define mmCP_HQD_DEQUEUE_REQUEST macro
H A Dgc_10_1_0_offset.h5347 #define mmCP_HQD_DEQUEUE_REQUEST macro
H A Dgc_10_3_0_offset.h4982 #define mmCP_HQD_DEQUEUE_REQUEST macro