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Searched refs:mmCP_ME2_PIPE0_INT_CNTL (Results 1 – 10 of 10) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h269 #define mmCP_ME2_PIPE0_INT_CNTL 0x3089 macro
H A Dgfx_7_2_d.h271 #define mmCP_ME2_PIPE0_INT_CNTL 0x3089 macro
H A Dgfx_8_0_d.h302 #define mmCP_ME2_PIPE0_INT_CNTL 0x3089 macro
H A Dgfx_8_1_d.h302 #define mmCP_ME2_PIPE0_INT_CNTL 0x3089 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2509 #define mmCP_ME2_PIPE0_INT_CNTL … macro
H A Dgc_9_2_1_offset.h2719 #define mmCP_ME2_PIPE0_INT_CNTL … macro
H A Dgc_9_1_offset.h2783 #define mmCP_ME2_PIPE0_INT_CNTL … macro
H A Dgc_10_1_0_offset.h4847 #define mmCP_ME2_PIPE0_INT_CNTL … macro
H A Dgc_10_3_0_offset.h4508 #define mmCP_ME2_PIPE0_INT_CNTL … macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v10_0.c9054 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); in gfx_v10_0_kiq_set_interrupt_state()