| /openbsd/sys/dev/pci/drm/amd/pm/powerplay/inc/ |
| H A D | polaris10_pwrvirus.h | 1505 { 0x54116f00, mmCP_MQD_BASE_ADDR },
1515 { 0x54117300, mmCP_MQD_BASE_ADDR },
1525 { 0x54117700, mmCP_MQD_BASE_ADDR },
1535 { 0x54117b00, mmCP_MQD_BASE_ADDR },
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| /openbsd/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_gfx_v8.c | 186 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++) in kgd_hqd_load()
187 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); in kgd_hqd_load()
201 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); in kgd_hqd_load()
252 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++) in kgd_hqd_dump()
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| H A D | amdgpu_amdkfd_gfx_v7.c | 176 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) in kgd_hqd_load()
177 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); in kgd_hqd_load()
228 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) in kgd_hqd_dump()
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| H A D | amdgpu_amdkfd_gfx_v10_3.c | 210 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in hqd_load_v10_3()
347 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in hqd_dump_v10_3()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 224 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_hqd_load()
361 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_hqd_dump()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 238 hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR); in kgd_gfx_v9_hqd_load()
374 for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR); in kgd_gfx_v9_hqd_dump()
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| H A D | mes_v10_1.c | 759 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
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| H A D | gfx_v7_0.c | 2988 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); in gfx_v7_0_mqd_commit()
2991 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) in gfx_v7_0_mqd_commit()
2992 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); in gfx_v7_0_mqd_commit()
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| H A D | gfx_v8_0.c | 4572 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); in gfx_v8_0_mqd_commit()
4586 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); in gfx_v8_0_mqd_commit()
4589 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) in gfx_v8_0_mqd_commit()
4590 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); in gfx_v8_0_mqd_commit()
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| H A D | gfx_v9_0.c | 3417 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, in gfx_v9_0_kiq_init_register()
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| H A D | gfx_v10_0.c | 6659 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, in gfx_v10_0_kiq_init_register()
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| /openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_7_0_d.h | 567 #define mmCP_MQD_BASE_ADDR 0x3245 macro
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| H A D | gfx_7_2_d.h | 580 #define mmCP_MQD_BASE_ADDR 0x3245 macro
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| H A D | gfx_8_0_d.h | 630 #define mmCP_MQD_BASE_ADDR 0x3245 macro
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| H A D | gfx_8_1_d.h | 630 #define mmCP_MQD_BASE_ADDR 0x3245 macro
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| /openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 2819 #define mmCP_MQD_BASE_ADDR … macro
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| H A D | gc_9_2_1_offset.h | 3003 #define mmCP_MQD_BASE_ADDR … macro
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| H A D | gc_9_1_offset.h | 3047 #define mmCP_MQD_BASE_ADDR … macro
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| H A D | gc_10_1_0_offset.h | 5301 #define mmCP_MQD_BASE_ADDR … macro
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| H A D | gc_10_3_0_offset.h | 4936 #define mmCP_MQD_BASE_ADDR … macro
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