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Searched refs:mmCP_RB1_BASE (Results 1 – 12 of 12) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h500 #define mmCP_RB1_BASE 0x3060 macro
H A Dgfx_7_0_d.h198 #define mmCP_RB1_BASE 0x3060 macro
H A Dgfx_7_2_d.h198 #define mmCP_RB1_BASE 0x3060 macro
H A Dgfx_8_0_d.h222 #define mmCP_RB1_BASE 0x3060 macro
H A Dgfx_8_1_d.h223 #define mmCP_RB1_BASE 0x3060 macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v6_0.c2174 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); in gfx_v6_0_cp_compute_resume()
H A Dgfx_v10_0.c6167 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); in gfx_v10_0_cp_gfx_resume()
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2448 #define mmCP_RB1_BASE … macro
H A Dgc_9_2_1_offset.h2663 #define mmCP_RB1_BASE … macro
H A Dgc_9_1_offset.h2725 #define mmCP_RB1_BASE … macro
H A Dgc_10_1_0_offset.h4789 #define mmCP_RB1_BASE … macro
H A Dgc_10_3_0_offset.h4442 #define mmCP_RB1_BASE … macro