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Searched refs:mmRLC_PG_CNTL (Results 1 – 14 of 14) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v7_0.c3667 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pu()
3673 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_sclk_slowdown_on_pu()
3681 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pd()
3687 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_sclk_slowdown_on_pd()
3700 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_cp_pg()
3713 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gds_pg()
3733 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gfx_cgpg()
3743 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gfx_cgpg()
3806 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gfx_static_mgpg()
3820 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gfx_dynamic_mgpg()
[all …]
H A Dgfx_v9_0.c2714 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_sck_slow_down_on_power_up()
2719 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_sck_slow_down_on_power_up()
2728 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_sck_slow_down_on_power_down()
2733 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_sck_slow_down_on_power_down()
2742 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_cp_power_gating()
2747 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_cp_power_gating()
2755 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_cg_power_gating()
2760 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_cg_power_gating()
2773 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_pipeline_powergating()
2790 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_static_mg_power_gating()
[all …]
H A Dgfx_v6_0.c2650 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_cp_pg()
2656 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_cp_pg()
2760 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_gfx_static_mgpg()
2766 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_gfx_static_mgpg()
2774 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_gfx_dynamic_mgpg()
2780 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_gfx_dynamic_mgpg()
H A Dgfx_v10_0.c5072 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); in gfx_v10_0_rlc_smu_handshake_cntl()
5086 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); in gfx_v10_0_rlc_smu_handshake_cntl()
5170 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); in gfx_v10_0_rlc_resume()
7951 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); in gfx_v10_cntl_power_gating()
7958 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); in gfx_v10_cntl_power_gating()
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h1165 #define mmRLC_PG_CNTL 0x30D7 macro
H A Dgfx_7_0_d.h1275 #define mmRLC_PG_CNTL 0x3103 macro
H A Dgfx_7_2_d.h1288 #define mmRLC_PG_CNTL 0x3103 macro
H A Dgfx_8_0_d.h1386 #define mmRLC_PG_CNTL 0xec43 macro
H A Dgfx_8_1_d.h1388 #define mmRLC_PG_CNTL 0xec43 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6037 #define mmRLC_PG_CNTL … macro
H A Dgc_9_2_1_offset.h6235 #define mmRLC_PG_CNTL … macro
H A Dgc_9_1_offset.h6259 #define mmRLC_PG_CNTL … macro
H A Dgc_10_1_0_offset.h9375 #define mmRLC_PG_CNTL … macro
H A Dgc_10_3_0_offset.h9205 #define mmRLC_PG_CNTL … macro