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Searched refs:uimm5 (Results 1 – 25 of 30) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo16Instr.td130 (outs mGPR:$rz), (ins mGPR:$rx, uimm5:$imm)>;
136 (outs), (ins mGPR:$rz, mGPR:$rx, uimm5:$imm)>;
161 def CMPNEI16 : I16_X_CMP<2, "cmpnei16", uimm5>;
454 defm : LdPat<extloadi8, uimm5, LD16B, i32>;
455 defm : LdPat<zextloadi8, uimm5, LD16B, i32>;
463 defm : StPat<truncstorei8, i32, uimm5, ST16B>;
543 def : Pat<(setne mGPR:$rs1, uimm5:$rs2),
545 def : Pat<(seteq mGPR:$rs1, uimm5:$rs2),
546 (MVCV16 (CMPNEI16 mGPR:$rs1, uimm5:$rs2))>;
710 (BCLRI16 mGPR:$rd, uimm5:$imm)>;
[all …]
H A DCSKYInstrInfo.td276 def uimm5 : uimm<5> {
388 let MIOperandInfo = (ops GPR, uimm5);
478 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
479 [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
481 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
482 [(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
484 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
485 [(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
487 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
573 def SEXT32 : I_5_XZ_U<0x16, (outs GPR:$rz), (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), "sext32", []>;
[all …]
H A DCSKYInstrAlias.td16 def : InstAlias<"bgeni16 $dst, $imm", (BGENI GPR:$dst, uimm5:$imm)>;
17 def : InstAlias<"bgeni32 $dst, $imm", (BGENI GPR:$dst, uimm5:$imm)>;
H A DCSKYInstrFormats16Instr.td173 AddrModeNone, (outs mGPR:$rz), (ins mGPR:$rx, uimm5:$imm5),
174 !strconcat(opstr, "\t$rz, $rx, $imm5"), [(set mGPR:$rz, (opnode mGPR:$rx, uimm5:$imm5))]> {
H A DCSKYInstrInfoF1.td18 let MIOperandInfo = (ops sFPR32, uimm5);
26 let MIOperandInfo = (ops sFPR64, uimm5);
/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td539 (ins GPR:$rd, GPR:$rj, uimm5:$msbw, uimm5:$lsbw),
543 (ins GPR:$rj, uimm5:$msbw, uimm5:$lsbw),
817 def : PatGprImm<rotr, ROTRI_W, uimm5>;
834 def : PatGprImm_32<rotr, ROTRI_W, uimm5>;
930 def : PatGprImm<shl, SLLI_W, uimm5>;
931 def : PatGprImm<sra, SRAI_W, uimm5>;
932 def : PatGprImm<srl, SRLI_W, uimm5>;
1184 def : Pat<(loongarch_bstrins GPR:$rd, GPR:$rj, uimm5:$msbd, uimm5:$lsbd),
1185 (BSTRINS_W GPR:$rd, GPR:$rj, uimm5:$msbd, uimm5:$lsbd)>;
1186 def : Pat<(loongarch_bstrpick GPR:$rj, uimm5:$msbd, uimm5:$lsbd),
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td567 (ins csr_sysreg:$imm12, uimm5:$rs1),
1058 (SLLIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>;
1060 (SRLIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>;
1062 (SRAIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>;
1666 : Pseudo<(outs), (ins uimm5:$val),
1683 : Pseudo<(outs GPR:$rd), (ins uimm5:$val),
1759 (SRLIW GPR:$rs1, uimm5:$shamt)>;
1762 def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
1763 (SRAIW GPR:$rs1, uimm5:$shamt)>;
1775 def : PatGprImm<binop_allwusers<shl>, SLLIW, uimm5>;
[all …]
H A DRISCVInstrInfoVVLPatterns.td399 // Give explicit Complexity to prefer simm5/uimm5.
576 !cast<ComplexPattern>(SplatPat#_#uimm5),
577 uimm5>;
997 wti.RegClass:$rs2, uimm5:$rs1, GPR:$vl, vti.Log2SEW)>;
1403 defm : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>;
1404 defm : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>;
1405 defm : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>;
2018 uimm5:$imm,
2084 uimm5:$imm,
2177 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2,
[all …]
H A DRISCVInstrInfoZb.td290 (ins GPR:$rs1, uimm5:$shamt), opcodestr,
506 (RORIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
544 def : PatGprImm<riscv_rorw, RORIW, uimm5>;
545 def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
546 (RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
755 def : Pat<(i64 (shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt)),
756 (SLLI_UW GPR:$rs1, uimm5:$shamt)>;
H A DRISCVInstrInfoV.td1134 defm VSLL_V : VSHT_IV_V_X_I<"vsll", 0b100101, uimm5>;
1135 defm VSRL_V : VSHT_IV_V_X_I<"vsrl", 0b101000, uimm5>;
1136 defm VSRA_V : VSHT_IV_V_X_I<"vsra", 0b101001, uimm5>;
1144 defm VNSRL_W : VNSHT_IV_V_X_I<"vnsrl", 0b101100, uimm5, "w">;
1145 defm VNSRA_W : VNSHT_IV_V_X_I<"vnsra", 0b101101, uimm5, "w">;
1294 defm VSSRL_V : VSSHF_IV_V_X_I<"vssrl", 0b101010, uimm5>;
1295 defm VSSRA_V : VSSHF_IV_V_X_I<"vssra", 0b101011, uimm5>;
1300 defm VNCLIP_W : VNCLP_IV_V_X_I<"vnclip", 0b101111, uimm5, "w">;
1640 defm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110, uimm5>;
1643 defm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111, uimm5>;
[all …]
H A DRISCVInstrInfoF.td454 def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, SysRegFRM.Encoding, uimm5:$imm)>;
455 def : InstAlias<"fsrmi $imm", (CSRRWI X0, SysRegFRM.Encoding, uimm5:$imm), 2>;
460 def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, SysRegFFLAGS.Encoding, uimm5:$imm)>;
461 def : InstAlias<"fsflagsi $imm", (CSRRWI X0, SysRegFFLAGS.Encoding, uimm5:$imm), 2>;
H A DRISCVInstrInfoVPseudos.td4553 Wti.RegClass, uimm5>;
5289 defm PseudoVSLL : VPseudoVSHT_VV_VX_VI<uimm5>;
5290 defm PseudoVSRL : VPseudoVSHT_VV_VX_VI<uimm5>;
5291 defm PseudoVSRA : VPseudoVSHT_VV_VX_VI<uimm5>;
5403 defm PseudoVSSRL : VPseudoVSSHT_VV_VX_VI<uimm5>;
5404 defm PseudoVSSRA : VPseudoVSSHT_VV_VX_VI<uimm5>;
5890 uimm5>;
5892 uimm5>;
5894 uimm5>;
6057 uimm5>;
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td139 def EXTUI : RRR_Inst<0x00, 0x04, 0x00, (outs AR:$r), (ins AR:$t, uimm5:$imm1, imm1_16:$imm2),
149 def SRAI : RRR_Inst<0x00, 0x01, 0x02, (outs AR:$r), (ins AR:$t, uimm5:$sa),
151 [(set AR:$r, (sra AR:$t, uimm5:$sa))]> {
181 def SSAI : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins uimm5:$imm),
367 (ins AR:$s, uimm5:$imm, brtarget:$target),
379 (ins AR:$s, uimm5:$imm, brtarget:$target),
H A DXtensaOperands.td61 // uimm5 predicate - Immediate in the range [0,31]
63 def uimm5 : Immediate<i32, [{ return Imm >= 0 && Imm <= 31; }], "Uimm5_AsmOperand"> {
/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMips64InstrInfo.td182 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
184 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
186 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
195 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
381 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5,
400 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64,
463 InstSE<(outs RO:$rt), (ins RO:$rs, uimm5:$pos, uimm5:$lenm1),
545 (ins GPR32Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
1032 (DINSM GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos,
1038 (DEXTM GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos,
[all …]
H A DMicroMipsInstrInfo.td510 InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
778 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
780 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
782 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
790 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
947 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
950 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1,
1381 (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1383 (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1385 (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
[all …]
H A DMipsInstrInfo.td640 // uimm4 < uimm5 < uimm6
643 // simm4 < uimm4 < simm5 < uimm5
648 // uimm5 < uimm5_plus1 (1..32) < uimm5_plus32 (32..63) < uimm6
650 // are not true supersets of uimm5 (but they are still subsets of uimm6).
654 // uimm5 < uimm5_64, and uimm5 < vsplat_uimm5
993 // Like uimm5 but reports a less confusing error for 32-63 when
1656 InstSE<(outs), (ins uimm5:$stype), "sync $stype",
2107 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
2109 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
2448 def INS : MMRel, StdMMR6Rel, InsBase<"ins", GPR32Opnd, uimm5,
[all …]
H A DMipsDSPInstrInfo.td314 dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
411 dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$shift_rs);
728 uimm5>,
737 uimm5>;
1099 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, uimm5, timmZExt5,
1105 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, uimm5,
H A DMicroMipsDSPInstrInfo.td235 "shll_s.w", int_mips_shll_s_w, immZExt5, NoItinerary, GPR32Opnd, uimm5>,
246 "shra_r.w", int_mips_shra_r_w, immZExt5, NoItinerary, GPR32Opnd, uimm5>;
292 dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$imm);
H A DMipsEVAInstrInfo.td171 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
H A DMicroMips32r6InstrInfo.td416 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
606 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
1149 dag InOperandList = (ins uimm5:$stype);
1292 dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_plus1:$size);
1303 dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_inssize_plus1:$size,
/openbsd/gnu/usr.bin/binutils-2.17/opcodes/
H A Dbfin-dis.c1366 OUTS (outf, uimm5 (src)); in decode_LOGI2op_0()
1374 OUTS (outf, uimm5 (src)); in decode_LOGI2op_0()
1382 OUTS (outf, uimm5 (src)); in decode_LOGI2op_0()
1390 OUTS (outf, uimm5 (src)); in decode_LOGI2op_0()
1398 OUTS (outf, uimm5 (src)); in decode_LOGI2op_0()
1405 OUTS (outf, uimm5 (src)); in decode_LOGI2op_0()
1411 OUTS (outf, uimm5 (src)); in decode_LOGI2op_0()
1417 OUTS (outf, uimm5 (src)); in decode_LOGI2op_0()
4087 OUTS (outf, uimm5 (immag)); in decode_dsp32shiftimm_0()
4097 OUTS (outf, uimm5 (immag)); in decode_dsp32shiftimm_0()
[all …]
/openbsd/gnu/usr.bin/binutils-2.17/gas/config/
H A Dbfin-parse.y213 #define uimm5(x) EXPR_VALUE (x) macro
2078 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2119 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2334 $$ = LOGI2OP ($3, uimm5 ($5), 4);
2346 $$ = LOGI2OP ($3, uimm5 ($5), 2);
2358 $$ = LOGI2OP ($3, uimm5 ($5), 3);
2369 $$ = LOGI2OP ($5, uimm5 ($7), 0);
2380 $$ = LOGI2OP ($5, uimm5 ($7), 1);
2741 $$ = LOGI2OP ($1, uimm5 ($3), 6);
2774 $$ = LOGI2OP ($1, uimm5 ($3), 7);
[all …]
/openbsd/gnu/usr.bin/binutils-2.17/gas/
H A Dbfin-parse.c604 #define uimm5(x) EXPR_VALUE (x) macro
4450 …(yyval.instr) = DSP32SHIFTIMM (1, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2…
4497 … (yyval.instr) = DSP32SHIFTIMM (0, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg),
4744 (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 4);
4757 (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 2);
4770 (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 3);
4783 (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 0);
4796 (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 1);
5231 (yyval.instr) = LOGI2OP ((yyvsp[-2].reg), uimm5 ((yyvsp[0].expr)), 6);
5270 (yyval.instr) = LOGI2OP ((yyvsp[-2].reg), uimm5 ((yyvsp[0].expr)), 7);
[all …]
/openbsd/gnu/usr.bin/binutils-2.17/cpu/
H A Dm32r.cpu472 (dnf f-uimm5 "uimm5" () 11 5)
667 (dnop uimm5 "5 bit shift count" (HASH-PREFIX) h-uint f-uimm5)
2022 (.str sym "i $dr,$uimm5")
2023 (+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)
2024 (set dr (sem-op dr uimm5))

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