| /qemu/target/sparc/ |
| H A D | win_helper.c | 270 target_ulong ccr = 0; in cpu_get_ccr() local
272 ccr |= (env->icc_C >> 32) & 1; in cpu_get_ccr()
273 ccr |= ((int32_t)env->cc_V < 0) << 1; in cpu_get_ccr()
274 ccr |= ((int32_t)env->icc_Z == 0) << 2; in cpu_get_ccr()
275 ccr |= ((int32_t)env->cc_N < 0) << 3; in cpu_get_ccr()
277 ccr |= env->xcc_C << 4; in cpu_get_ccr()
278 ccr |= (env->cc_V < 0) << 5; in cpu_get_ccr()
279 ccr |= (env->xcc_Z == 0) << 6; in cpu_get_ccr()
280 ccr |= (env->cc_N < 0) << 7; in cpu_get_ccr()
282 return ccr; in cpu_get_ccr()
|
| /qemu/hw/gpio/ |
| H A D | zaurus.c | 46 uint16_t ccr; member
93 return s->ccr; in scoop_read()
134 s->ccr = value; in scoop_write()
237 VMSTATE_UINT16(ccr, ScoopInfo),
|
| /qemu/hw/i2c/ |
| H A D | allwinner-i2c.c | 186 s->ccr = TWI_CCR_RESET; in allwinner_i2c_reset_hold()
256 value = s->ccr; in allwinner_i2c_read()
384 s->ccr = value & TWI_CCR_MASK; in allwinner_i2c_write()
422 VMSTATE_UINT8(ccr, AWI2CState),
|
| /qemu/linux-user/ppc/ |
| H A D | signal.c | 247 uint32_t ccr = 0; in save_user_regs() local
262 ccr = ppc_get_cr(env); in save_user_regs()
263 __put_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]); in save_user_regs()
332 target_ulong ccr; in restore_user_regs() local
351 __get_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]); in restore_user_regs()
352 ppc_set_cr(env, ccr); in restore_user_regs()
|
| H A D | target_syscall.h | 38 abi_ulong ccr; member
|
| /qemu/target/arm/tcg/ |
| H A D | hflags.c | 101 uint32_t ccr = env->v7m.ccr[env->v7m.secure]; in rebuild_hflags_m32() local
104 if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { in rebuild_hflags_m32()
119 (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { in rebuild_hflags_m32()
|
| H A D | m_helper.c | 1006 (env->v7m.ccr[is_secure] & R_V7M_CCR_STKOFHFNMIGN_MASK); in v7m_update_fpccr()
1206 (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKALIGN_MASK)) { in v7m_push_stack()
1505 !(env->v7m.ccr[env->v7m.secure] & in do_v7m_exception_exit()
2159 if (env->v7m.ccr[M_REG_S] & R_V7M_CCR_TRD_MASK) { in v7m_handle_execute_nsc()
|
| H A D | op_helper.c | 140 && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { in handle_possible_div0_trap()
|
| /qemu/include/hw/i2c/ |
| H A D | allwinner-i2c.h | 53 uint8_t ccr; member
|
| /qemu/target/m68k/ |
| H A D | helper.c | 1303 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t ccr) in cpu_m68k_set_ccr() argument
1305 env->cc_x = (ccr & CCF_X ? 1 : 0); in cpu_m68k_set_ccr()
1306 env->cc_n = (ccr & CCF_N ? -1 : 0); in cpu_m68k_set_ccr()
1307 env->cc_z = (ccr & CCF_Z ? 0 : 1); in cpu_m68k_set_ccr()
1308 env->cc_v = (ccr & CCF_V ? -1 : 0); in cpu_m68k_set_ccr()
1309 env->cc_c = (ccr & CCF_C ? 1 : 0); in cpu_m68k_set_ccr()
1313 void HELPER(set_ccr)(CPUM68KState *env, uint32_t ccr) in HELPER()
1315 cpu_m68k_set_ccr(env, ccr); in HELPER()
|
| H A D | translate.c | 2150 TCGv ccr; in gen_get_sr() local
2153 ccr = gen_get_ccr(s); in gen_get_sr()
2156 tcg_gen_or_i32(sr, sr, ccr); in gen_get_sr()
2585 TCGv ccr; in DISAS_INSN() local
2587 ccr = gen_get_ccr(s); in DISAS_INSN()
2588 DEST_EA(env, insn, OS_WORD, ccr, NULL); in DISAS_INSN()
2881 TCGv ccr; in DISAS_INSN() local
2885 ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s)); in DISAS_INSN()
2890 gen_set_sr(s, ccr, true); in DISAS_INSN()
|
| /qemu/target/ppc/ |
| H A D | arch_dump.c | 41 reg_t ccr; member
127 reg->ccr = cpu_to_dump_reg(s, cr); in ppc_write_elf_prstatus()
|
| /qemu/hw/display/ |
| H A D | pxa2xx_lcd.c | 69 uint32_t ccr; member
781 return s->ccr; in pxa2xx_lcdc_read()
921 if (!(s->ccr & CCR_CEN) && (value & CCR_CEN)) { in pxa2xx_lcdc_write()
925 s->ccr = value & 0x81ffffe7; in pxa2xx_lcdc_write()
1408 VMSTATE_UINT32(ccr, PXA2xxLCDState),
|
| /qemu/hw/intc/ |
| H A D | armv7m_nvic.c | 1112 val = cpu->env.v7m.ccr[attrs.secure]; in nvic_readl()
1113 val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; in nvic_readl()
1693 cpu->env.v7m.ccr[M_REG_NS] = in nvic_writel()
1694 (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK) in nvic_writel()
1704 value |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; in nvic_writel()
1708 cpu->env.v7m.ccr[attrs.secure] = value; in nvic_writel()
2162 return s->cpu->env.v7m.ccr[attrs.secure] & R_V7M_CCR_USERSETMPEND_MASK; in nvic_user_access_ok()
|
| /qemu/hw/sh4/ |
| H A D | sh7750.c | 81 uint32_t ccr; member
300 return s->ccr; in sh7750_mem_readl()
457 s->ccr = mem_value; in sh7750_mem_writel()
|
| /qemu/target/arm/ |
| H A D | cpu.c | 422 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; in arm_cpu_reset_hold()
423 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; in arm_cpu_reset_hold()
426 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; in arm_cpu_reset_hold()
427 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; in arm_cpu_reset_hold()
430 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; in arm_cpu_reset_hold()
431 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; in arm_cpu_reset_hold()
|
| H A D | machine.c | 404 VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU),
601 VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU),
|
| H A D | cpu.h | 546 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ member
|
| /qemu/include/hw/ppc/ |
| H A D | spapr_nested.h | 400 uint64_t ccr; member
|
| /qemu/target/sh4/ |
| H A D | helper.c | 761 if (!(env->ccr & 1)) in cpu_sh4_is_cached()
|
| /qemu/hw/ppc/ |
| H A D | spapr_nested.c | 396 l2_state.cr = regs->ccr; in h_enter_nested()
546 regs->ccr = l2_state.cr; in spapr_exit_nested_hv()
|
| /qemu/pc-bios/ |
| H A D | canyonlands.dts | 271 ccr = <0x00001000>;
|
| /qemu/linux-user/ |
| H A D | elfload.c | 1208 target_ulong ccr = 0; in elf_core_copy_regs() local
1220 ccr = ppc_get_cr(env); in elf_core_copy_regs()
1221 (*regs)[38] = tswapreg(ccr); in elf_core_copy_regs()
|
| /qemu/target/cris/ |
| H A D | translate_v10.c.inc | 35 "$wz", "$ccr", "$p6-prefix", "$mof",
|