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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrFormats.td12 bits <5> Vu32;
14 bits <5> Rt32;
20 bits <7> Ii;
22 bits <5> Rs32;
24 bits <2> Pd4;
32 bits <2> Pd4;
36 bits <11> Ii;
41 bits <5> n1;
56 bits <2> Ii;
59 bits <6> II;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFormats.td57 bits<3> rd;
58 bits<3> rt;
59 bits<3> rs;
71 bits<3> rd;
72 bits<3> rs;
84 bits<3> rt;
85 bits<3> rs;
96 bits<3> rd;
97 bits<3> rt;
110 bits<3> rd;
[all …]
H A DMipsMSAInstrFormats.td33 bits<3> m;
46 bits<4> m;
82 class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
93 class MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
104 class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
115 class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
126 class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
139 class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
152 class MSA_3R_INDEX_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
351 class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
[all …]
H A DMicroMips32r6InstrFormats.td47 bits<3> rs;
58 bits<5> rs;
68 bits<5> rt;
69 bits<5> rs;
81 bits<5> rt;
82 bits<5> rs;
104 bits<2> rt;
116 bits<5> rd;
117 bits<5> rt;
143 bits<5> rd;
[all …]
H A DMipsInstrFormats.td188 class MFC3OP_FM<bits<6> op, bits<5> mfmt, bits<3> guest> : StdArch {
189 bits<5> rt;
190 bits<5> rd;
204 class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch {
216 class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
217 bits<5> rd;
289 class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
350 class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
442 class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
681 class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
[all …]
H A DMicroMipsDSPInstrFormats.td25 bits<5> rd;
26 bits<5> rs;
27 bits<5> rt;
37 bits<5> rt;
38 bits<5> rs;
48 bits<5> rt;
49 bits<5> rs;
50 bits<2> ac;
61 bits<5> rd;
62 bits<5> rs;
[all …]
H A DMips32r6InstrFormats.td177 bits<5> rs;
178 bits<5> rt;
205 bits<5> rt;
220 bits<5> fs;
221 bits<5> fd;
234 bits<5> ft;
235 bits<5> fs;
236 bits<5> fd;
249 bits<5> ft;
261 bits<5> ct;
[all …]
H A DMipsDSPInstrFormats.td66 bits<5> rd;
67 bits<5> rs;
68 bits<5> rt;
80 bits<5> rd;
81 bits<5> rs;
94 bits<5> rs;
95 bits<5> rt;
107 bits<5> rs;
108 bits<5> rt;
109 bits<5> rd;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrFormats.td79 bits<11> src0;
81 bits<11> src1;
85 bits<1> last;
115 bits<11> dst;
118 bits<1> clamp;
137 bits<2> omod;
150 bits<11> src2;
167 bits<11> src2;
370 bits<2> COND;
408 bits<2> COND;
[all …]
/freebsd/contrib/gdtoa/
H A Dstrtordd.c51 L[_0] = (bits[2] >> 21) | (bits[3] << 11 & 0xfffff)
63 bits[1] = bits[1] << i | bits[0] >> (32-i);
64 bits[0] = bits[0] << i & (ULong)0xffffffffL;
76 bits[1] = bits[0] >> (32 - i);
77 bits[0] = bits[0] << i & (ULong)0xffffffffL;
80 bits[1] = bits[0] << (i - 32);
108 L[_0] = ((bits[3] << i | bits[2] >> j) & 0xfffff)
110 L[_1] = (bits[2] << i | bits[1] >> j) & 0xffffffffL;
136 L[_1] = (bits[1] << i | bits[0] >> j) & 0xffffffffL;
145 L[_1] = (bits[1] << i | bits[0] >> j) & 0xffffffffL;
[all …]
H A Dstrtopdd.c46 ULong bits[4]; local
69 u->L[_1] = (bits[1] >> 21 | bits[2] << 11) & 0xffffffffL;
70 u->L[_0] = (bits[2] >> 21) | ((bits[3] << 11) & 0xfffff)
82 bits[1] = bits[1] << i | bits[0] >> (32-i);
83 bits[0] = bits[0] << i & 0xffffffffL;
95 bits[1] = bits[0] >> (32 - i);
96 bits[0] = bits[0] << i & 0xffffffffL;
99 bits[1] = bits[0] << (i - 32);
112 if (bits[3])
127 u->L[_0] = ((bits[3] << i | bits[2] >> j) & 0xfffff)
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td49 // 32 bits to 64 bits.
54 // 32 bits to 64 bits.
143 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
166 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
223 class SCForm<bits<6> opcode, bits<1> xo1, bits<1> xo2,
849 class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo,
1226 class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
1553 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
1562 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
1569 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
[all …]
/freebsd/sys/fs/nfs/
H A Dnfs.h429 (t)->bits[0] = (f)->bits[0]; \
430 (t)->bits[1] = (f)->bits[1]; \
431 (t)->bits[2] = (f)->bits[2]; \
451 (b)->bits[0] &= ~((a)->bits[0]); \
452 (b)->bits[1] &= ~((a)->bits[1]); \
453 (b)->bits[2] &= ~((a)->bits[2]); \
457 (b)->bits[0] &= ((a)->bits[0]); \
486 (b)->bits[1] == (p)->bits[1] && (b)->bits[2] == (p)->bits[2])
573 (t)->bits[0] = (f)->bits[0]; \
574 (t)->bits[1] = (f)->bits[1]; \
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td28 bits<5> rs1;
29 bits<5> rs2;
43 bits<10> imm;
44 bits<5> rd;
59 bits<5> rs2;
60 bits<5> rs1;
71 bits<3> rd;
84 bits<3> rd;
108 class RVInst16CA<bits<6> funct6, bits<2> funct2, bits<2> opcode, dag outs,
149 class RVInst16CU<bits<6> funct6, bits<5> funct5, bits<2> opcode, dag outs,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLASXInstrFormats.td25 bits<5> xd;
37 bits<5> xj;
38 bits<5> xd;
49 bits<5> rj;
50 bits<5> xd;
61 bits<5> xj;
62 bits<3> cd;
75 bits<5> xj;
76 bits<5> xd;
90 bits<5> xj;
[all …]
H A DLoongArchLSXInstrFormats.td25 bits<5> vd;
37 bits<5> vj;
38 bits<5> vd;
49 bits<5> rj;
50 bits<5> vd;
61 bits<5> vj;
62 bits<3> cd;
75 bits<5> vj;
76 bits<5> vd;
89 bits<5> rj;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124-peripherals-opp.dtsi9 opp-hz = /bits/ 64 <12750000>;
15 opp-hz = /bits/ 64 <12750000>;
21 opp-hz = /bits/ 64 <12750000>;
27 opp-hz = /bits/ 64 <12750000>;
33 opp-hz = /bits/ 64 <20400000>;
39 opp-hz = /bits/ 64 <20400000>;
45 opp-hz = /bits/ 64 <20400000>;
51 opp-hz = /bits/ 64 <20400000>;
57 opp-hz = /bits/ 64 <40800000>;
63 opp-hz = /bits/ 64 <40800000>;
[all …]
H A Dtegra30-peripherals-opp.dtsi59 opp-hz = /bits/ 64 <12750000>;
66 opp-hz = /bits/ 64 <12750000>;
73 opp-hz = /bits/ 64 <12750000>;
80 opp-hz = /bits/ 64 <25500000>;
87 opp-hz = /bits/ 64 <25500000>;
94 opp-hz = /bits/ 64 <25500000>;
101 opp-hz = /bits/ 64 <27000000>;
108 opp-hz = /bits/ 64 <27000000>;
115 opp-hz = /bits/ 64 <27000000>;
122 opp-hz = /bits/ 64 <51000000>;
[all …]
/freebsd/lib/msun/src/
H A Ds_remquol.c74 sx = ux.bits.sign; in remquol()
80 if((uy.bits.exp|uy.bits.manh|uy.bits.manl)==0 || /* y=0 */ in remquol()
83 ((uy.bits.manh&~LDBL_NBIT)|uy.bits.manl)!=0)) /* or y is NaN */ in remquol()
85 if(ux.bits.exp<=uy.bits.exp) { in remquol()
86 if((ux.bits.exp<uy.bits.exp) || in remquol()
87 (ux.bits.manh<=uy.bits.manh && in remquol()
88 (ux.bits.manh<uy.bits.manh || in remquol()
89 ux.bits.manl<uy.bits.manl))) { in remquol()
93 if(ux.bits.manh==uy.bits.manh && ux.bits.manl==uy.bits.manl) { in remquol()
118 lx = ux.bits.manl; in remquol()
[all …]
H A De_fmodl.c71 sx = ux.bits.sign; in fmodl()
74 if((uy.bits.exp|uy.bits.manh|uy.bits.manl)==0 || /* y=0 */ in fmodl()
77 ((uy.bits.manh&~LDBL_NBIT)|uy.bits.manl)!=0)) /* or y is NaN */ in fmodl()
79 if(ux.bits.exp<=uy.bits.exp) { in fmodl()
80 if((ux.bits.exp<uy.bits.exp) || in fmodl()
81 (ux.bits.manh<=uy.bits.manh && in fmodl()
82 (ux.bits.manh<uy.bits.manh || in fmodl()
83 ux.bits.manl<uy.bits.manl))) { in fmodl()
86 if(ux.bits.manh==uy.bits.manh && ux.bits.manl==uy.bits.manl) { in fmodl()
110 lx = ux.bits.manl; in fmodl()
[all …]
H A Ds_nextafterl.c39 ((ux.bits.manh&~LDBL_NBIT)|ux.bits.manl) != 0) || in nextafterl()
41 ((uy.bits.manh&~LDBL_NBIT)|uy.bits.manl) != 0)) in nextafterl()
46 ux.bits.manl = 1; in nextafterl()
47 ux.bits.sign = uy.bits.sign; in nextafterl()
52 if(ux.bits.manl==0) { in nextafterl()
54 ux.bits.exp -= 1; in nextafterl()
55 ux.bits.manh = (ux.bits.manh - 1) | (ux.bits.manh & LDBL_NBIT); in nextafterl()
57 ux.bits.manl -= 1; in nextafterl()
59 ux.bits.manl += 1; in nextafterl()
61 ux.bits.manh = (ux.bits.manh + 1) | (ux.bits.manh & LDBL_NBIT); in nextafterl()
[all …]
H A Ds_floorl.c31 u.bits.manh += (c); \
33 u.bits.exp++; \
41 u.bits.exp++; \
59 (u.bits.manh | u.bits.manl) != 0) in floorl()
63 if (((u.bits.manh & m) | u.bits.manl) == 0) in floorl()
65 if (u.bits.sign) { in floorl()
68 u.bits.exp++; in floorl()
74 u.bits.manh &= ~m; in floorl()
75 u.bits.manl = 0; in floorl()
82 if (u.bits.sign) { in floorl()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/leds/
H A Dleds-lp55xx.txt41 clock-mode = /bits/ 8 <2>;
44 led-cur = /bits/ 8 <0x2f>;
45 max-cur = /bits/ 8 <0x5f>;
50 led-cur = /bits/ 8 <0x2f>;
51 max-cur = /bits/ 8 <0x5f>;
55 led-cur = /bits/ 8 <0x2f>;
56 max-cur = /bits/ 8 <0x5f>;
75 clock-mode = /bits/ 8 <1>;
79 led-cur = /bits/ 8 <0x14>;
80 max-cur = /bits/ 8 <0x20>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra132-peripherals-opp.dtsi10 opp-hz = /bits/ 64 <12750000>;
16 opp-hz = /bits/ 64 <12750000>;
22 opp-hz = /bits/ 64 <12750000>;
28 opp-hz = /bits/ 64 <12750000>;
34 opp-hz = /bits/ 64 <20400000>;
40 opp-hz = /bits/ 64 <20400000>;
46 opp-hz = /bits/ 64 <20400000>;
52 opp-hz = /bits/ 64 <20400000>;
58 opp-hz = /bits/ 64 <40800000>;
64 opp-hz = /bits/ 64 <40800000>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td45 class RRR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
48 bits<4> r;
49 bits<4> s;
50 bits<4> t;
63 bits<4> r;
64 bits<4> s;
65 bits<4> t;
102 class RSR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
126 class CALLX_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
160 class BRI12_Inst<bits<4> op0, bits<2> n, bits<2> m, dag outs, dag ins,
[all …]

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