Searched refs:reset_mask (Results 1 – 11 of 11) sorted by relevance
1757 u32 reset_mask = 0; in cayman_gpu_check_soft_reset() local1768 reset_mask |= RADEON_RESET_GFX; in cayman_gpu_check_soft_reset()1772 reset_mask |= RADEON_RESET_CP; in cayman_gpu_check_soft_reset()1780 reset_mask |= RADEON_RESET_DMA; in cayman_gpu_check_soft_reset()1801 reset_mask |= RADEON_RESET_IH; in cayman_gpu_check_soft_reset()1814 reset_mask |= RADEON_RESET_MC; in cayman_gpu_check_soft_reset()1830 return reset_mask; in cayman_gpu_check_soft_reset()1839 if (reset_mask == 0) in cayman_gpu_soft_reset()1967 u32 reset_mask; in cayman_asic_reset() local1976 if (reset_mask) in cayman_asic_reset()[all …]
1608 u32 reset_mask = 0; in r600_gpu_check_soft_reset() local1631 reset_mask |= RADEON_RESET_CP; in r600_gpu_check_soft_reset()1639 reset_mask |= RADEON_RESET_DMA; in r600_gpu_check_soft_reset()1644 reset_mask |= RADEON_RESET_RLC; in r600_gpu_check_soft_reset()1647 reset_mask |= RADEON_RESET_IH; in r600_gpu_check_soft_reset()1661 reset_mask |= RADEON_RESET_MC; in r600_gpu_check_soft_reset()1672 return reset_mask; in r600_gpu_check_soft_reset()1681 if (reset_mask == 0) in r600_gpu_soft_reset()1874 u32 reset_mask; in r600_asic_reset() local1883 if (reset_mask) in r600_asic_reset()[all …]
3809 u32 reset_mask = 0; in evergreen_gpu_check_soft_reset() local3819 reset_mask |= RADEON_RESET_GFX; in evergreen_gpu_check_soft_reset()3823 reset_mask |= RADEON_RESET_CP; in evergreen_gpu_check_soft_reset()3831 reset_mask |= RADEON_RESET_DMA; in evergreen_gpu_check_soft_reset()3844 reset_mask |= RADEON_RESET_IH; in evergreen_gpu_check_soft_reset()3857 reset_mask |= RADEON_RESET_MC; in evergreen_gpu_check_soft_reset()3873 return reset_mask; in evergreen_gpu_check_soft_reset()3882 if (reset_mask == 0) in evergreen_gpu_soft_reset()4034 u32 reset_mask; in evergreen_asic_reset() local4043 if (reset_mask) in evergreen_asic_reset()[all …]
3762 u32 reset_mask = 0; in si_gpu_check_soft_reset() local3773 reset_mask |= RADEON_RESET_GFX; in si_gpu_check_soft_reset()3777 reset_mask |= RADEON_RESET_CP; in si_gpu_check_soft_reset()3785 reset_mask |= RADEON_RESET_RLC; in si_gpu_check_soft_reset()3809 reset_mask |= RADEON_RESET_IH; in si_gpu_check_soft_reset()3822 reset_mask |= RADEON_RESET_MC; in si_gpu_check_soft_reset()3838 return reset_mask; in si_gpu_check_soft_reset()3847 if (reset_mask == 0) in si_gpu_soft_reset()4075 u32 reset_mask; in si_asic_reset() local4084 if (reset_mask) in si_asic_reset()[all …]
171 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_dma_is_lockup() local173 if (!(reset_mask & RADEON_RESET_DMA)) { in evergreen_dma_is_lockup()
4879 u32 reset_mask = 0; in cik_gpu_check_soft_reset() local4890 reset_mask |= RADEON_RESET_GFX; in cik_gpu_check_soft_reset()4893 reset_mask |= RADEON_RESET_CP; in cik_gpu_check_soft_reset()4898 reset_mask |= RADEON_RESET_RLC; in cik_gpu_check_soft_reset()4922 reset_mask |= RADEON_RESET_IH; in cik_gpu_check_soft_reset()4935 reset_mask |= RADEON_RESET_MC; in cik_gpu_check_soft_reset()4946 return reset_mask; in cik_gpu_check_soft_reset()4963 if (reset_mask == 0) in cik_gpu_soft_reset()5246 u32 reset_mask; in cik_asic_reset() local5255 if (reset_mask) in cik_asic_reset()[all …]
43 u32 reset_mask = si_gpu_check_soft_reset(rdev); in si_dma_is_lockup() local51 if (!(reset_mask & mask)) { in si_dma_is_lockup()
208 u32 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_dma_is_lockup() local210 if (!(reset_mask & RADEON_RESET_DMA)) { in r600_dma_is_lockup()
287 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_dma_is_lockup() local295 if (!(reset_mask & mask)) { in cayman_dma_is_lockup()
775 u32 reset_mask = cik_gpu_check_soft_reset(rdev); in cik_sdma_is_lockup() local783 if (!(reset_mask & mask)) { in cik_sdma_is_lockup()
372 static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask) in gen6_reset_pm_iir() argument378 I915_WRITE(reg, reset_mask); in gen6_reset_pm_iir()379 I915_WRITE(reg, reset_mask); in gen6_reset_pm_iir()