Searched refs:family (Results 1 – 25 of 283) sorted by path
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/dragonfly/contrib/binutils-2.27/ |
H A D | COPYING3 | 298 tangible personal property which is normally used for personal, family,
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/dragonfly/contrib/binutils-2.27/bfd/ |
H A D | COPYING | 298 tangible personal property which is normally used for personal, family,
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/dragonfly/contrib/binutils-2.27/binutils/doc/ |
H A D | binutils.texi | 2249 disassembly for the e300 family. @option{440} selects disassembly for 4879 processor family from the name of the particular @sc{cpu}.
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/dragonfly/contrib/binutils-2.27/gas/ |
H A D | COPYING | 298 tangible personal property which is normally used for personal, family,
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/dragonfly/contrib/binutils-2.27/gas/doc/ |
H A D | as.texinfo | 119 @subtitle for the @value{TARGET} family 746 This option is accepted but has no effect on the @value{TARGET} family. 902 processor family. 934 configured for the Blackfin processor family. 940 the Blackfin processor family. 1107 Specify which processor in the M32R family is the target. The default 1133 Specify what processor in the 68000 family is the target. The default 1646 processor family. 1750 a Z80 family processor. 1864 @sc{gnu} @command{as} is really a family of assemblers. [all …]
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H A D | c-alpha.texi | 335 The Alpha family uses both @sc{ieee} and VAX floating-point numbers.
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H A D | c-arm.texi | 582 The ARM family uses @sc{ieee} floating-point numbers.
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H A D | c-bfin.texi | 233 The Blackfin family has no hardware floating point but the .float
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H A D | c-h8300.texi | 143 The H8/300 family has no hardware floating point, but the @code{.float} 163 for the H8/300 family. 168 for the H8/300 family. 173 the usual (16-bit) for the H8/300 family. 178 the usual (16-bit) for the H8/300 family. 181 On the H8/300 family (including the H8/300H) @samp{.word} directives 196 pseudo-instructions are needed on this family.
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H A D | c-hppa.texi | 74 The HPPA family uses @sc{ieee} floating-point numbers.
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H A D | c-i386.texi | 843 The @samp{rex} family of prefixes is used by x86-64 to encode
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H A D | c-m32c.texi | 17 the Renesas M32C family. Normally the default is to assemble code for 117 address into a 16 bit register. While the M32C family only has 24
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H A D | c-m32r.texi | 37 Renesas M32R family. Normally the default is to assemble code for
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H A D | c-m68hc11.texi | 63 co-processor featured on some S12X-family chips. 452 Here, @samp{jb@var{XX}} stands for an entire family of pseudo-operations, 454 list of pseudo-ops in this family is:
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H A D | c-m68k.texi | 156 Motorola 680x0 family. The default depends upon how @code{@value{AS}} 160 addressing modes are permitted. The members of the 680x0 family are 209 Assemble for the CPU32 family of chips. 225 Assemble for the ColdFire family of chips. 539 Here, @samp{j@var{XX}} stands for an entire family of pseudo-operations, 541 list of pseudo-ops in this family is: 563 The full family of pseudo-operations covered here is 592 This family includes
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H A D | c-microblaze.texi | 15 The Xilinx MicroBlaze processor family includes several variants, all using
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H A D | c-msp430.texi | 266 The MSP 430 family uses @sc{ieee} 32-bit floating-point numbers. 320 additional pseudo-instructions are needed on this family.
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H A D | c-nds32.texi | 17 The NDS32 processors family includes high-performance and low-power 32-bit
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H A D | c-ppc.texi | 29 The PowerPC chip family includes several successive levels, using the same 115 Generate code for PowerPC e300 family.
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H A D | c-sh.texi | 23 (formerly Hitachi) / SuperH SH family. 237 pseudo-instructions are needed on this family. Note, however, that
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H A D | c-sparc.texi | 30 The SPARC chip family includes several successive versions, using the same
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H A D | c-v850.texi | 22 for the V850 processor family: 282 The V850 family uses @sc{ieee} floating-point numbers.
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H A D | c-xtensa.texi | 311 The @code{LOOP} family of instructions must be aligned such that the
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H A D | c-z80.texi | 70 The assembler syntax closely follows the 'Z80 family CPU User Manual' by
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H A D | c-z8k.texi | 15 The Z8000 @value{AS} supports both members of the Z8000 family: the
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