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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/llvm-ir/
H A Dstore.ll75 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
83 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
103 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
111 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
185 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
193 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
213 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
299 ; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
307 ; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
445 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/Mips/llvm-ir/
H A Dstore.ll75 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
83 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
103 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
111 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
185 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
193 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
213 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
299 ; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
307 ; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
445 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/Mips/llvm-ir/
H A Dstore.ll75 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
83 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
103 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
111 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
185 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
193 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
213 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
299 ; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
307 ; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
445 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Mips/llvm-ir/
H A Dstore.ll75 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
83 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
103 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
111 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
185 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
193 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
213 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
295 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
303 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
437 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/Mips/llvm-ir/
H A Dstore.ll75 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
83 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
103 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
111 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
185 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
193 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
213 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
299 ; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
307 ; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
445 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/llvm-ir/
H A Dstore.ll75 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
83 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
103 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
111 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
185 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
193 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
213 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
295 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
303 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
437 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
[all …]
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/gas/testsuite/gas/mips/
H A Dmicromips-size-1.s106 dsll32 $2, $3, 5 # No way to force 32-bit DSLL.
109 dsll32 $2, $3, 13 # No way to force 32-bit DSLL.
112 dsll32 $10, $11, 5 # No way to force 32-bit DSLL.
H A Dmicromips-size-0.s129 dsll32 $2, $3, 5 # No way to force 32-bit DSLL.
134 dsll32 $2, $3, 13 # No way to force 32-bit DSLL.
139 dsll32 $10, $11, 5 # No way to force 32-bit DSLL.
/dports/lang/gnatdroid-binutils/binutils-2.27/gas/testsuite/gas/mips/
H A Dmicromips-size-1.s106 dsll32 $2, $3, 5 # No way to force 32-bit DSLL.
109 dsll32 $2, $3, 13 # No way to force 32-bit DSLL.
112 dsll32 $10, $11, 5 # No way to force 32-bit DSLL.
H A Dmicromips-size-0.s129 dsll32 $2, $3, 5 # No way to force 32-bit DSLL.
134 dsll32 $2, $3, 13 # No way to force 32-bit DSLL.
139 dsll32 $10, $11, 5 # No way to force 32-bit DSLL.
/dports/devel/arm-elf-binutils/binutils-2.37/gas/testsuite/gas/mips/
H A Dmicromips-size-1.s114 dsll32 $2, $3, 5 # No way to force 32-bit DSLL.
117 dsll32 $2, $3, 13 # No way to force 32-bit DSLL.
120 dsll32 $10, $11, 5 # No way to force 32-bit DSLL.
H A Dmicromips-size-0.s129 dsll32 $2, $3, 5 # No way to force 32-bit DSLL.
134 dsll32 $2, $3, 13 # No way to force 32-bit DSLL.
139 dsll32 $10, $11, 5 # No way to force 32-bit DSLL.
/dports/devel/gnulibiberty/binutils-2.37/gas/testsuite/gas/mips/
H A Dmicromips-size-1.s114 dsll32 $2, $3, 5 # No way to force 32-bit DSLL.
117 dsll32 $2, $3, 13 # No way to force 32-bit DSLL.
120 dsll32 $10, $11, 5 # No way to force 32-bit DSLL.
H A Dmicromips-size-0.s129 dsll32 $2, $3, 5 # No way to force 32-bit DSLL.
134 dsll32 $2, $3, 13 # No way to force 32-bit DSLL.
139 dsll32 $10, $11, 5 # No way to force 32-bit DSLL.
/dports/devel/binutils/binutils-2.37/gas/testsuite/gas/mips/
H A Dmicromips-size-1.s114 dsll32 $2, $3, 5 # No way to force 32-bit DSLL.
117 dsll32 $2, $3, 13 # No way to force 32-bit DSLL.
120 dsll32 $10, $11, 5 # No way to force 32-bit DSLL.
H A Dmicromips-size-0.s129 dsll32 $2, $3, 5 # No way to force 32-bit DSLL.
134 dsll32 $2, $3, 13 # No way to force 32-bit DSLL.
139 dsll32 $10, $11, 5 # No way to force 32-bit DSLL.
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Mips/cheri/
H A Daddrfolder-bad-killed-reg6.mir86 ; CHECK: [[DSLL:%[0-9]+]]:gpr64 = DSLL killed [[CAPLOAD16_]], 2
94 …; CHECK: CAPSTORE32 killed $zero, [[DSLL]], 0, [[CIncOffsetImm]] :: (store 4 into %ir.2, addrspa…
102 %5:gpr64 = DSLL killed %4, 2
H A Daddrfolder-bad-killed-reg7.mir109 ; CHECK: [[DSLL:%[0-9]+]]:gpr64 = DSLL killed [[CAPLOAD16_]], 3
110 ; CHECK: [[CIncOffset:%[0-9]+]]:cherigpr = CIncOffset [[LOADCAP_BigImm]], [[DSLL]]
114 …; CHECK: [[CAPLOAD3264_:%[0-9]+]]:gpr64 = CAPLOAD3264 [[DSLL]], 0, [[CIncOffsetImm]] :: (load 4 …
127 %6:gpr64 = DSLL killed %5, 3
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Mips/
H A Dfcopysign-f32-f64.ll46 ; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
47 ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Mips/
H A Dfcopysign-f32-f64.ll46 ; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
47 ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Mips/
H A Dfcopysign-f32-f64.ll46 ; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
47 ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Mips/
H A Dfcopysign-f32-f64.ll46 ; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
47 ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/
H A Dfcopysign-f32-f64.ll46 ; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
47 ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Mips/
H A Dfcopysign-f32-f64.ll46 ; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
47 ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/
H A Dfcopysign-f32-f64.ll46 ; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
47 ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]

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