/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/ |
H A D | Lan91xDxeHw.h | 96 #define EPHSR_LINK_OK BIT14 105 #define RCR_FILT_CAR BIT14 138 #define CTR_RCV_BAD BIT14 173 #define PTR_AUTO_INCR BIT14 190 #define MGMT_MSK_CRS100 BIT14 203 #define RX_BROADCAST BIT14 245 #define PHYCR_LOOPBK BIT14 // Set loopback mode 258 #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/ |
H A D | Lan91xDxeHw.h | 96 #define EPHSR_LINK_OK BIT14 105 #define RCR_FILT_CAR BIT14 138 #define CTR_RCV_BAD BIT14 173 #define PTR_AUTO_INCR BIT14 190 #define MGMT_MSK_CRS100 BIT14 203 #define RX_BROADCAST BIT14 245 #define PHYCR_LOOPBK BIT14 // Set loopback mode 258 #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability
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/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/EmbeddedPkg/Drivers/Lan91xDxe/ |
H A D | Lan91xDxeHw.h | 96 #define EPHSR_LINK_OK BIT14 105 #define RCR_FILT_CAR BIT14 138 #define CTR_RCV_BAD BIT14 173 #define PTR_AUTO_INCR BIT14 190 #define MGMT_MSK_CRS100 BIT14 203 #define RX_BROADCAST BIT14 245 #define PHYCR_LOOPBK BIT14 // Set loopback mode 258 #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/ |
H A D | Lan91xDxeHw.h | 96 #define EPHSR_LINK_OK BIT14 105 #define RCR_FILT_CAR BIT14 138 #define CTR_RCV_BAD BIT14 173 #define PTR_AUTO_INCR BIT14 190 #define MGMT_MSK_CRS100 BIT14 203 #define RX_BROADCAST BIT14 245 #define PHYCR_LOOPBK BIT14 // Set loopback mode 258 #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/ARM/VExpressPkg/Drivers/Lan91xDxe/ |
H A D | Lan91xDxeHw.h | 103 #define EPHSR_LINK_OK BIT14 112 #define RCR_FILT_CAR BIT14 145 #define CTR_RCV_BAD BIT14 180 #define PTR_AUTO_INCR BIT14 197 #define MGMT_MSK_CRS100 BIT14 210 #define RX_BROADCAST BIT14 252 #define PHYCR_LOOPBK BIT14 // Set loopback mode 265 #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability
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/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
H A D | PchRegsPcu.h | 89 #define B_PCH_LPC_DEV_STS_SSE BIT14 // Signaled System Error 196 #define B_PCH_LPC_FWH_BIOS_DEC_EF0 BIT14 // F0-F8 Enable 484 #define B_PCH_ACPI_PM1_WAK_DIS_PCIE0 BIT14 // PCI Express 0 Disable 557 #define B_PCH_SMI_EN_PERIODIC BIT14 // Periodic Enable 592 #define B_PCH_SMI_STS_PERIODIC BIT14 // Periodic Status 763 #define B_PCH_PMC_FUNC_DIS_OTG BIT14 // USB OTG Disable 802 #define B_PCH_PMC_GPI_ROUT_7 (BIT15 | BIT14) 856 #define B_PCH_PMC_PSS_PG_STS_OTG VCCA BIT14 // OTG VCCA 886 #define B_PCH_PMC_D3_STS_0_OTG BIT14 // OTG 923 #define B_PCH_PMC_D3_STDBY_STS_0_OTG BIT14 // OTG [all …]
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H A D | PchRegsSpi.h | 47 #define B_PCH_SPI_HSFS_FDV BIT14 // Flash Descriptor Valid 76 #define B_PCH_SPI_OPTYPE7_MASK (BIT15 | BIT14) // Opcode Type 7 Mask 97 #define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) // Flash Descriptor Section Se…
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H A D | PchRegsSata.h | 81 #define B_PCH_SATA_PCISTS_SSE BIT14 // Signaled System Error 170 #define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) /… 171 #define B_PCH_SATA_PORT6_DISABLED BIT14 187 #define B_PCH_SATA_PCS_PORT6_DET BIT14 // Port 6 Present
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
H A D | PchRegsPcu.h | 83 #define B_PCH_LPC_DEV_STS_SSE BIT14 // Signaled System Error 190 #define B_PCH_LPC_FWH_BIOS_DEC_EF0 BIT14 // F0-F8 Enable 478 #define B_PCH_ACPI_PM1_WAK_DIS_PCIE0 BIT14 // PCI Express 0 Disable 551 #define B_PCH_SMI_EN_PERIODIC BIT14 // Periodic Enable 586 #define B_PCH_SMI_STS_PERIODIC BIT14 // Periodic Status 757 #define B_PCH_PMC_FUNC_DIS_OTG BIT14 // USB OTG Disable 796 #define B_PCH_PMC_GPI_ROUT_7 (BIT15 | BIT14) 850 #define B_PCH_PMC_PSS_PG_STS_OTG VCCA BIT14 // OTG VCCA 880 #define B_PCH_PMC_D3_STS_0_OTG BIT14 // OTG 917 #define B_PCH_PMC_D3_STDBY_STS_0_OTG BIT14 // OTG [all …]
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H A D | PchRegsSpi.h | 41 #define B_PCH_SPI_HSFS_FDV BIT14 // Flash Descriptor Valid 70 #define B_PCH_SPI_OPTYPE7_MASK (BIT15 | BIT14) // Opcode Type 7 Mask 91 #define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) // Flash Descriptor Section Se…
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H A D | PchRegsSata.h | 75 #define B_PCH_SATA_PCISTS_SSE BIT14 // Signaled System Error 164 #define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) /… 165 #define B_PCH_SATA_PORT6_DISABLED BIT14 181 #define B_PCH_SATA_PCS_PORT6_DET BIT14 // Port 6 Present
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/ |
H A D | PchRegsFia.h | 62 #define B_PCH_FIA_PCR_L3O (BIT15 | BIT14 | BIT13 | BIT12) 70 #define B_PCH_FIA_PCR_L11O (BIT15 | BIT14 | BIT13 | BIT12) 78 #define B_PCH_FIA_PCR_L19O (BIT15 | BIT14 | BIT13 | BIT12) 86 #define B_PCH_FIA_PCR_L27O (BIT15 | BIT14 | BIT13 | BIT12)
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H A D | PchRegsHsio.h | 41 #define B_HSIO_PCR_ACCESS_TYPE (BIT15 | BIT14) 43 #define V_HSIO_PCR_ACCESS_TYPE_BDCAST (BIT15 | BIT14) 86 #define B_HSIO_PCR_RX_DWORD12_O_CFGEWMARGINSEL BIT14 111 #define B_HSIO_PCR_RX_DWORD34_MM_PH_OFC_SCALE_2_0 (BIT14 | BIT13 | BIT12)
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H A D | PchRegsPcie.h | 147 #define B_PCH_PCIE_CFG_MPC_PCIESD (BIT14 | BIT13) 199 #define B_PCH_PCIE_CFG_STRPFUSECFG_RPC (BIT15 | BIT14) 247 #define B_PCH_PCIE_CFG_EX_LECTL_UPTPH (BIT14 | BIT13 | BIT12) 278 #define B_PCH_PCIE_CFG_PCIEDBG_CTONFAE BIT14 433 #define B_PCH_PCIE_CFG_EQCFG2_HAPCSB (BIT15 | BIT14 | BIT13 | BIT12) 455 #define B_SPX_PCR_PCD_RP4FN (BIT14 | BIT13 | BIT12) ///< Port 4 Function Number 474 #define B_SPX_PCR_PCIEHBP_CRCSEL (BIT15 | BIT14) ///< CRC select
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H A D | PchRegsPmc.h | 56 #define B_ACPI_IO_PM1_STS_PCIEXP_WAKE_STS BIT14 106 #define B_ACPI_IO_SMI_EN_PERIODIC BIT14 146 #define B_ACPI_IO_SMI_STS_PERIODIC BIT14 208 #define B_ACPI_IO_OC_WDT_CTL_EN BIT14 377 #define B_PMC_PWRM_GEN_PMCON_A_PWR_FLR BIT14 437 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_XHCI BIT14 ///< xHCI ModPHY SPD RT Request 497 #define B_PMC_PWRM_S5_PWRGATE_POL_S5AC_GATE_SUS BIT14 ///< Deep S… 622 #define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_D0_FDIS_PMC BIT14 ///< PCIe Controller D Port 0 Fu… 648 #define B_PMC_PWRM_FUSE_DIS_RD_2_ICC_FUSE_SS_DIS BIT14 ///< ICC Fuse or Soft Strap Disab…
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/Include/ |
H A D | QuarkNcSocId.h | 291 #define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN BIT14 440 #define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0) 442 #define B_QNC_PM1BLK_PM1S_PCIEWSTS (BIT14) 451 #define B_QNC_PM1BLK_PM1E_PWAKED (BIT14) 475 #define B_QNC_GPE0BLK_GPE0S_GPIO (BIT14) // GPIO 482 #define B_QNC_GPE0BLK_GPE0E_GPIO (BIT14) // GPIO 653 #define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12) //L0 Exit latency mask 684 #define B_QNC_PCIE_CCFG_UPRS (BIT14) // Upstream Posted Request Size 723 #define B_QNC_RCRB_SPIC_DC (BIT14) // SPI Data Cycle Enable
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/ |
H A D | PchRegsPmc.h | 82 #define B_PCH_PMC_GEN_PMCON_B_SUS_PWR_FLR BIT14 113 #define B_PCH_PMC_BM_CX_CNF_PHOLD_BM_STS_BLOCK BIT14 130 #define B_PCH_ACPI_PM1_STS_PCIEXP_WAKE_STS BIT14 148 #define B_PCH_ACPI_PM1_EN_PCIEXP_WAKE_DIS BIT14 182 #define B_PCH_SMI_EN_PERIODIC BIT14 222 #define B_PCH_SMI_STS_PERIODIC BIT14 284 #define B_PCH_OC_WDT_CTL_EN BIT14 452 #define B_PCH_PWRM_S5AC_GATE_SUS BIT14 ///< Deep S… 528 #define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XHCI BIT14 ///< xHCI ModPHY SPD RT Request 601 #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D0_FUSE_DIS BIT14 ///< PCIe Controller D Port 0 Fus… [all …]
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H A D | PchRegsThermal.h | 73 #define B_PCH_TBAR_TSPM_DTSSS0EN BIT14 80 #define R_PCH_TBAR_TL2_PMCTEN BIT14 88 #define B_PCH_TBAR_TL2_PMCTEN BIT14
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H A D | PchRegsFia.h | 86 #define B_PCH_PCR_FIA_L3O (BIT15 | BIT14 | BIT13 | BIT12) 94 #define B_PCH_PCR_FIA_L11O (BIT15 | BIT14 | BIT13 | BIT12) 102 #define B_PCH_PCR_FIA_L19O (BIT15 | BIT14 | BIT13 | BIT12) 110 #define B_PCH_PCR_FIA_L27O (BIT15 | BIT14 | BIT13 | BIT12)
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H A D | PchRegsPcie.h | 187 #define B_PCH_PCIE_MPC_PCIESD (BIT14 | BIT13) 239 #define B_PCH_PCIE_STRPFUSECFG_RPC (BIT15 | BIT14) 288 #define B_PCH_PCIE_EX_LECTL_UPTPH (BIT14 | BIT13 | BIT12) 318 #define B_PCH_PCIE_PCIEDBG_CTONFAE BIT14 456 #define B_PCH_PCIE_EQCFG2_HAPCSB (BIT15 | BIT14 | BIT13 | BIT12) 488 #define B_PCH_PCR_SPX_PCD_RP4FN (BIT14 | BIT13 | BIT12) ///< Port 4 Function Numb… 507 #define B_PCH_PCR_SPX_PCIEHBP_CRCSEL (BIT15 | BIT14) ///< CRC select
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H A D | PchRegsHsio.h | 11 #define B_PCH_HSIO_ACCESS_TYPE (BIT15 | BIT14) 13 #define V_PCH_HSIO_ACCESS_TYPE_BDCAST (BIT15 | BIT14) 60 #define B_PCH_HSIO_RX_DWORD12_O_CFGEWMARGINSEL BIT14 87 #define B_PCH_HSIO_RX_DWORD34_MM_PH_OFC_SCALE_2_0 (BIT14 | BIT13 | BIT12)
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/SimicsIch10Pkg/Include/Register/ |
H A D | PchRegsPmc.h | 83 #define B_PCH_PMC_GEN_PMCON_B_SUS_PWR_FLR BIT14 114 #define B_PCH_PMC_BM_CX_CNF_PHOLD_BM_STS_BLOCK BIT14 131 #define B_PCH_ACPI_PM1_STS_PCIEXP_WAKE_STS BIT14 149 #define B_PCH_ACPI_PM1_EN_PCIEXP_WAKE_DIS BIT14 183 #define B_PCH_SMI_EN_PERIODIC BIT14 223 #define B_PCH_SMI_STS_PERIODIC BIT14 285 #define B_PCH_OC_WDT_CTL_EN BIT14 453 #define B_PCH_PWRM_S5AC_GATE_SUS BIT14 ///< Deep S… 529 #define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XHCI BIT14 ///< xHCI ModPHY SPD RT Request 602 #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D0_FUSE_DIS BIT14 ///< PCIe Controller D Port 0 Fus… [all …]
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/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/EmbeddedPkg/Drivers/Lan9118Dxe/ |
H A D | Lan9118DxeHw.h | 99 #define IRQCFG_INT_DEAS_CLR BIT14 // Clear the deassertion coun… 112 #define INSTS_RXE BIT14 // Receiver Error 154 #define PHYCR_LOOPBK BIT14 // Set loopback mode 167 #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability 237 #define TXCFG_TXD_DUMP BIT14 // Clear Tx Data FIFO
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/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
H A D | Lan9118DxeHw.h | 164 #define IRQCFG_INT_DEAS_CLR BIT14 // Clear the deassertion coun… 177 #define INSTS_RXE BIT14 // Receiver Error 219 #define PHYCR_LOOPBK BIT14 // Set loopback mode 232 #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability 302 #define TXCFG_TXD_DUMP BIT14 // Clear Tx Data FIFO
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
H A D | Lan9118DxeHw.h | 164 #define IRQCFG_INT_DEAS_CLR BIT14 // Clear the deassertion coun… 177 #define INSTS_RXE BIT14 // Receiver Error 219 #define PHYCR_LOOPBK BIT14 // Set loopback mode 232 #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability 302 #define TXCFG_TXD_DUMP BIT14 // Clear Tx Data FIFO
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