| /dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Omap35xxPkg/Include/Omap3530/ |
| H A D | Omap3530Prcm.h | 43 #define CM_FCLKEN1_CORE_EN_I2C1_MASK BIT15
45 #define CM_FCLKEN1_CORE_EN_I2C1_ENABLE BIT15
47 #define CM_ICLKEN1_CORE_EN_I2C1_MASK BIT15
49 #define CM_ICLKEN1_CORE_EN_I2C1_ENABLE BIT15
118 #define CM_FCLKEN_PER_EN_GPIO4_ENABLE BIT15
143 #define CM_ICLKEN_PER_EN_GPIO4_ENABLE BIT15
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/TexasInstruments/Omap35xxPkg/Include/Omap3530/ |
| H A D | Omap3530Prcm.h | 37 #define CM_FCLKEN1_CORE_EN_I2C1_MASK BIT15
39 #define CM_FCLKEN1_CORE_EN_I2C1_ENABLE BIT15
41 #define CM_ICLKEN1_CORE_EN_I2C1_MASK BIT15
43 #define CM_ICLKEN1_CORE_EN_I2C1_ENABLE BIT15
112 #define CM_FCLKEN_PER_EN_GPIO4_ENABLE BIT15
137 #define CM_ICLKEN_PER_EN_GPIO4_ENABLE BIT15
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| /dports/emulators/qemu42/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/ |
| H A D | Lan91xDxeHw.h | 78 #define TCR_SWFDUP BIT15
106 #define RCR_SOFT_RST BIT15
126 #define CR_EPH_POWER_EN BIT15
167 #define FIFO_REMPTY BIT15
174 #define PTR_RCV BIT15
204 #define RX_ALGN_ERR BIT15
246 #define PHYCR_RESET BIT15 // Do a PHY reset
259 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/ |
| H A D | Lan91xDxeHw.h | 78 #define TCR_SWFDUP BIT15
106 #define RCR_SOFT_RST BIT15
126 #define CR_EPH_POWER_EN BIT15
167 #define FIFO_REMPTY BIT15
174 #define PTR_RCV BIT15
204 #define RX_ALGN_ERR BIT15
246 #define PHYCR_RESET BIT15 // Do a PHY reset
259 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
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| /dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/EmbeddedPkg/Drivers/Lan91xDxe/ |
| H A D | Lan91xDxeHw.h | 78 #define TCR_SWFDUP BIT15
106 #define RCR_SOFT_RST BIT15
126 #define CR_EPH_POWER_EN BIT15
167 #define FIFO_REMPTY BIT15
174 #define PTR_RCV BIT15
204 #define RX_ALGN_ERR BIT15
246 #define PHYCR_RESET BIT15 // Do a PHY reset
259 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/ |
| H A D | Lan91xDxeHw.h | 78 #define TCR_SWFDUP BIT15
106 #define RCR_SOFT_RST BIT15
126 #define CR_EPH_POWER_EN BIT15
167 #define FIFO_REMPTY BIT15
174 #define PTR_RCV BIT15
204 #define RX_ALGN_ERR BIT15
246 #define PHYCR_RESET BIT15 // Do a PHY reset
259 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/ARM/VExpressPkg/Drivers/Lan91xDxe/ |
| H A D | Lan91xDxeHw.h | 85 #define TCR_SWFDUP BIT15
113 #define RCR_SOFT_RST BIT15
133 #define CR_EPH_POWER_EN BIT15
174 #define FIFO_REMPTY BIT15
181 #define PTR_RCV BIT15
211 #define RX_ALGN_ERR BIT15
253 #define PHYCR_RESET BIT15 // Do a PHY reset
266 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
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| /dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| H A D | Lan9118DxeHw.h | 73 #define RXSTATUS_ES BIT15 // Reports any error from b…
86 #define TXSTATUS_ES BIT15 // Reports any errors from …
113 #define INSTS_RWT BIT15 // Packet > 2048 bytes receiv…
155 #define PHYCR_RESET BIT15 // Do a PHY reset
168 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
209 #define MACCR_HO BIT15 // Hash Only Filtering Mode
228 #define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs
238 #define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO
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| /dports/emulators/qemu42/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| H A D | Lan9118DxeHw.h | 138 #define RXSTATUS_ES BIT15 // Reports any error from b…
151 #define TXSTATUS_ES BIT15 // Reports any errors from …
178 #define INSTS_RWT BIT15 // Packet > 2048 bytes receiv…
220 #define PHYCR_RESET BIT15 // Do a PHY reset
233 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
274 #define MACCR_HO BIT15 // Hash Only Filtering Mode
293 #define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs
303 #define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| H A D | Lan9118DxeHw.h | 138 #define RXSTATUS_ES BIT15 // Reports any error from b…
151 #define TXSTATUS_ES BIT15 // Reports any errors from …
178 #define INSTS_RWT BIT15 // Packet > 2048 bytes receiv…
220 #define PHYCR_RESET BIT15 // Do a PHY reset
233 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
274 #define MACCR_HO BIT15 // Hash Only Filtering Mode
293 #define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs
303 #define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO
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| /dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| H A D | Lan9118DxeHw.h | 138 #define RXSTATUS_ES BIT15 // Reports any error from b…
151 #define TXSTATUS_ES BIT15 // Reports any errors from …
178 #define INSTS_RWT BIT15 // Packet > 2048 bytes receiv…
220 #define PHYCR_RESET BIT15 // Do a PHY reset
233 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
274 #define MACCR_HO BIT15 // Hash Only Filtering Mode
293 #define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs
303 #define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| H A D | Lan9118DxeHw.h | 138 #define RXSTATUS_ES BIT15 // Reports any error from b…
151 #define TXSTATUS_ES BIT15 // Reports any errors from …
178 #define INSTS_RWT BIT15 // Packet > 2048 bytes receiv…
220 #define PHYCR_RESET BIT15 // Do a PHY reset
233 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
274 #define MACCR_HO BIT15 // Hash Only Filtering Mode
293 #define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs
303 #define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/ARM/VExpressPkg/Drivers/Lan9118Dxe/ |
| H A D | Lan9118DxeHw.h | 145 #define RXSTATUS_ES BIT15 // Reports any error from b…
158 #define TXSTATUS_ES BIT15 // Reports any errors from …
185 #define INSTS_RWT BIT15 // Packet > 2048 bytes receiv…
227 #define PHYCR_RESET BIT15 // Do a PHY reset
240 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
281 #define MACCR_HO BIT15 // Hash Only Filtering Mode
300 #define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs
310 #define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO
|
| /dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| H A D | PchRegsSpi.h | 46 #define B_PCH_SPI_HSFS_FLOCKDN BIT15 // Flash Configuration Lock-Down
62 #define B_PCH_SPI_PR0_RPE BIT15 // Read Protection Enable
68 #define B_PCH_SPI_PR1_RPE BIT15 // Read Protection Enable
76 #define B_PCH_SPI_OPTYPE7_MASK (BIT15 | BIT14) // Opcode Type 7 Mask
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| H A D | PchRegsPcu.h | 88 #define B_PCH_LPC_DEV_STS_DPE BIT15 // Detected Parity Error
195 #define B_PCH_LPC_FWH_BIOS_DEC_EF8 BIT15 // F8-FF Enable
464 #define B_PCH_ACPI_PM1_STS_WAK BIT15 // Wake Status
591 #define B_PCH_SMI_STS_ILB BIT15 // ILB SMI Status
701 #define B_PCH_PMC_GEN_PMCON_PME_B0_S5_DIS BIT15 // PME B0 S5 Disable
762 #define B_PCH_PMC_FUNC_DIS_USH BIT15 // USH (USB3) Disable
802 #define B_PCH_PMC_GPI_ROUT_7 (BIT15 | BIT14)
855 #define B_PCH_PMC_PSS_PG_STS_OTG_VCCACLK BIT15 // OTG VCCACLK
885 #define B_PCH_PMC_D3_STS_0_USH BIT15 // USH
922 #define B_PCH_PMC_D3_STDBY_STS_0_USH BIT15 // USH
[all …]
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| H A D | PchRegsSpi.h | 40 #define B_PCH_SPI_HSFS_FLOCKDN BIT15 // Flash Configuration Lock-Down
56 #define B_PCH_SPI_PR0_RPE BIT15 // Read Protection Enable
62 #define B_PCH_SPI_PR1_RPE BIT15 // Read Protection Enable
70 #define B_PCH_SPI_OPTYPE7_MASK (BIT15 | BIT14) // Opcode Type 7 Mask
|
| H A D | PchRegsPcu.h | 82 #define B_PCH_LPC_DEV_STS_DPE BIT15 // Detected Parity Error
189 #define B_PCH_LPC_FWH_BIOS_DEC_EF8 BIT15 // F8-FF Enable
458 #define B_PCH_ACPI_PM1_STS_WAK BIT15 // Wake Status
585 #define B_PCH_SMI_STS_ILB BIT15 // ILB SMI Status
695 #define B_PCH_PMC_GEN_PMCON_PME_B0_S5_DIS BIT15 // PME B0 S5 Disable
756 #define B_PCH_PMC_FUNC_DIS_USH BIT15 // USH (USB3) Disable
796 #define B_PCH_PMC_GPI_ROUT_7 (BIT15 | BIT14)
849 #define B_PCH_PMC_PSS_PG_STS_OTG_VCCACLK BIT15 // OTG VCCACLK
879 #define B_PCH_PMC_D3_STS_0_USH BIT15 // USH
916 #define B_PCH_PMC_D3_STDBY_STS_0_USH BIT15 // USH
[all …]
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/ |
| H A D | PchRegsFia.h | 47 #define B_PCH_PCR_FIA_CC_SCPTCGE BIT15
86 #define B_PCH_PCR_FIA_L3O (BIT15 | BIT14 | BIT13 | BIT12)
94 #define B_PCH_PCR_FIA_L11O (BIT15 | BIT14 | BIT13 | BIT12)
102 #define B_PCH_PCR_FIA_L19O (BIT15 | BIT14 | BIT13 | BIT12)
110 #define B_PCH_PCR_FIA_L27O (BIT15 | BIT14 | BIT13 | BIT12)
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| H A D | PchRegsThermal.h | 74 #define B_PCH_TBAR_TSPM_TSPMLOCK BIT15
79 #define R_PCH_TBAR_TL2_LOCK BIT15
82 #define B_PCH_TBAR_PHLE BIT15
|
| H A D | PchRegsPmc.h | 81 #define B_PCH_PMC_GEN_PMCON_B_PME_B0_S5_DIS BIT15
112 #define B_PCH_PMC_BM_CX_CNF_SCRATCHPAD BIT15
129 #define B_PCH_ACPI_PM1_STS_WAK BIT15
221 #define B_PCH_SMI_STS_SERIRQ BIT15
283 #define B_PCH_OC_WDT_CTL_FORCE_ALL BIT15
451 #define B_PCH_PWRM_S5DC_GATE_SUS BIT15 ///< Deep S…
485 #define B_PCH_PWRM_PMSYNC_PM_SYNC_LOCK BIT15 ///< PM_SYN…
527 #define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XDCI BIT15 ///< xDCI ModPHY SPD RT Request
600 #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D1_FUSE_DIS BIT15 ///< PCIe Controller D Port 1 Fus…
625 #define B_PCH_PWRM_FUSE_DIS_RD_2_SATA_FUSE_SS_DIS BIT15 ///< SATA Fuse or Soft Strap Disa…
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| H A D | PchRegsPcie.h | 185 #define B_PCH_PCIE_MPC_CCEL (BIT17 | BIT16 | BIT15)
217 #define B_PCH_PCIE_PWRCTL_DBUPI BIT15
239 #define B_PCH_PCIE_STRPFUSECFG_RPC (BIT15 | BIT14)
375 #define B_PCH_PCIE_EQCFG1_RTPCOE BIT15
456 #define B_PCH_PCIE_EQCFG2_HAPCSB (BIT15 | BIT14 | BIT13 | BIT12)
489 #define B_PCH_PCR_SPX_PCD_RP4CH BIT15 ///< Port 4 config hide
507 #define B_PCH_PCR_SPX_PCIEHBP_CRCSEL (BIT15 | BIT14) ///< CRC select
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/ |
| H A D | PchRegsFia.h | 62 #define B_PCH_FIA_PCR_L3O (BIT15 | BIT14 | BIT13 | BIT12)
70 #define B_PCH_FIA_PCR_L11O (BIT15 | BIT14 | BIT13 | BIT12)
78 #define B_PCH_FIA_PCR_L19O (BIT15 | BIT14 | BIT13 | BIT12)
86 #define B_PCH_FIA_PCR_L27O (BIT15 | BIT14 | BIT13 | BIT12)
|
| H A D | PchRegsPcie.h | 145 #define B_PCH_PCIE_CFG_MPC_CCEL (BIT17 | BIT16 | BIT15)
177 #define B_PCH_PCIE_CFG_PWRCTL_DBUPI BIT15
199 #define B_PCH_PCIE_CFG_STRPFUSECFG_RPC (BIT15 | BIT14)
315 #define B_PCH_PCIE_CFG_LTROVR_LTRSROVR BIT15 ///< LTR Snoop Requirement Bit Override
352 #define B_PCH_PCIE_CFG_EQCFG1_RTPCOE BIT15
433 #define B_PCH_PCIE_CFG_EQCFG2_HAPCSB (BIT15 | BIT14 | BIT13 | BIT12)
456 #define B_SPX_PCR_PCD_RP4CH BIT15 ///< Port 4 config hide
474 #define B_SPX_PCR_PCIEHBP_CRCSEL (BIT15 | BIT14) ///< CRC select
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| H A D | PchRegsPmc.h | 55 #define B_ACPI_IO_PM1_STS_WAK BIT15
145 #define B_ACPI_IO_SMI_STS_SERIRQ BIT15
207 #define B_ACPI_IO_OC_WDT_CTL_FORCE_ALL BIT15
226 #define B_ACPI_IO_GPE0_STS_127_96_GPIO_TIER_2 BIT15
376 #define B_PMC_PWRM_GEN_PMCON_A_PME_B0_S5_DIS BIT15
436 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_XDCI BIT15 ///< xDCI ModPHY SPD RT Request
496 #define B_PMC_PWRM_S5_PWRGATE_POL_S5DC_GATE_SUS BIT15 ///< Deep S…
534 #define B_PMC_PWRM_PMSYNC_PM_SYNC_LOCK BIT15 ///< PM_SYN…
621 #define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_D1_FDIS_PMC BIT15 ///< PCIe Controller D Port 1 Fu…
647 #define B_PMC_PWRM_FUSE_DIS_RD_2_SATA_FUSE_SS_DIS BIT15 ///< SATA Fuse or Soft Strap Disa…
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/SimicsIch10Pkg/Include/Register/ |
| H A D | PchRegsPmc.h | 82 #define B_PCH_PMC_GEN_PMCON_B_PME_B0_S5_DIS BIT15
113 #define B_PCH_PMC_BM_CX_CNF_SCRATCHPAD BIT15
130 #define B_PCH_ACPI_PM1_STS_WAK BIT15
222 #define B_PCH_SMI_STS_SERIRQ BIT15
284 #define B_PCH_OC_WDT_CTL_FORCE_ALL BIT15
452 #define B_PCH_PWRM_S5DC_GATE_SUS BIT15 ///< Deep S…
486 #define B_PCH_PWRM_PMSYNC_PM_SYNC_LOCK BIT15 ///< PM_SYN…
528 #define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XDCI BIT15 ///< xDCI ModPHY SPD RT Request
601 #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D1_FUSE_DIS BIT15 ///< PCIe Controller D Port 1 Fus…
626 #define B_PCH_PWRM_FUSE_DIS_RD_2_SATA_FUSE_SS_DIS BIT15 ///< SATA Fuse or Soft Strap Disa…
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