| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| H A D | meminit.c | 620 …PHY, (COMPEN1CH0 + (channel_i * DDRCOMP_CH_OFFSET)), (BIT19|BIT17), ((BIT31|BIT30)|BIT19… in ddrphy_init()
638 …CH0 + (channel_i * DDRCOMP_CH_OFFSET)), (BIT31|(0x0A<<16)), (BIT31|(BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
639 …CH0 + (channel_i * DDRCOMP_CH_OFFSET)), (BIT31|(0x0A<<16)), (BIT31|(BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
640 …CH0 + (channel_i * DDRCOMP_CH_OFFSET)), (BIT31|(0x10<<16)), (BIT31|(BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
641 …CH0 + (channel_i * DDRCOMP_CH_OFFSET)), (BIT31|(0x10<<16)), (BIT31|(BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
647 …CH0 + (channel_i * DDRCOMP_CH_OFFSET)), (BIT31|(0x0A<<16)), (BIT31|(BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
1262 isbM32m(DDRPHY, B0LATCTL0, val << 16, (BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)); in rcvn_cal()
1273 isbM32m(DDRPHY, B1LATCTL0, val << 16, (BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)); in rcvn_cal()
1276 isbM32m(DDRPHY, B01LATCTL1, val << 16, (BIT20|BIT19|BIT18|BIT17|BIT16)); in rcvn_cal()
2135 …((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10))); // Override: DIFFA… in set_auto_refresh()
[all …]
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| H A D | general_definitions.h | 30 #undef BIT19
66 #define BIT19 0x00080000U macro
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/ |
| H A D | PchRegsUsb.h | 53 #define B_PCH_XHCI_XHCC1_IIL1E (BIT21 | BIT20 | BIT19)
55 #define V_PCH_XHCI_XHCC1_IIL1E_32 (BIT19)
57 #define V_PCH_XHCI_XHCC1_IIL1E_128 (BIT20 | BIT19)
59 #define V_PCH_XHCI_XHCC1_IIL1E_512 (BIT21 | BIT19)
61 #define V_PCH_XHCI_XHCC1_IIL1E_131072 (BIT21 | BIT20 | BIT19)
86 #define B_PCH_XHCI_XHCLKGTEN_SSTCGE (BIT19 | BIT18 | BIT17 | BIT16)
265 #define B_PCH_XHCI_PORTSCXUSB2_WRC BIT19 ///< Warm Port Reset Change
284 #define B_PCH_XHCI_PORTSCXUSB3_WRC BIT19 ///< Warm Port Reset Change
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| H A D | PchRegsFia.h | 87 #define B_PCH_PCR_FIA_L4O (BIT19 | BIT18 | BIT17 | BIT16)
95 #define B_PCH_PCR_FIA_L12O (BIT19 | BIT18 | BIT17 | BIT16)
103 #define B_PCH_PCR_FIA_L20O (BIT19 | BIT18 | BIT17 | BIT16)
111 #define B_PCH_PCR_FIA_L28O (BIT19 | BIT18 | BIT17 | BIT16)
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| H A D | PchRegsHsio.h | 109 #define B_PCH_HSIO_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BI…
115 #define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BI…
124 #define B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BI…
153 #define B_PCH_HSIO_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BI…
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| H A D | PchRegsPmc.h | 109 #define B_PCH_PMC_BM_CX_CNF_DPSN_BREAK_EN BIT19
121 #define B_PCH_PMC_ETR3_SKIP_HOST_RST_HS BIT19
217 #define B_PCH_SMI_STS_PATCH BIT19
421 #define B_PCH_PWRM_CFG_SSMAW_MASK (BIT19 | BIT18) ///< SLP_SU…
422 #define V_PCH_PWRM_CFG_SSMAW_4S (BIT19 | BIT18) ///< 4 seco…
423 #define V_PCH_PWRM_CFG_SSMAW_1S BIT19 ///< 1 seco…
596 #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E1_FUSE_DIS BIT19 ///< PCIe Controller E Port 1 Fus…
621 #define B_PCH_PWRM_FUSE_DIS_RD_2_OTG_FUSE_SS_DIS BIT19 ///< OTG Fuse or Soft Strap Disab…
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| H A D | PchRegsSata.h | 170 #define B_PCH_H_SATA_MAP_SPD3 BIT19
188 #define B_PCH_H_SATA_PCS_P3P BIT19
338 #define B_PCH_SATA_AHCI_CAP_SNZO BIT19
386 #define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SGPIO BIT19
511 #define B_PCH_SATA_AHCI_PxCMD_MASK (BIT27 | BIT26 | BIT22 | BIT21 | BIT19 | BIT18)
533 #define B_PCH_SATA_AHCI_PxCMD_MPSP BIT19 ///< Mechanical Switch Attached to Port
617 #define B_PCH_SATA_AHCI_PXSERR_10B8B_DECERR BIT19
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| H A D | PchRegsPcie.h | 183 #define B_PCH_PCIE_MPC_UCEL (BIT20 | BIT19 | BIT18)
335 #define B_PCH_PCIE_PCIESTS1_LNKSTAT (BIT22 | BIT21 | BIT20 | BIT19)
424 #define B_PCH_PCIE_HAEQ_MACFOMC BIT19
454 #define B_PCH_PCIE_EQCFG2_PCET (BIT19 | BIT18 | BIT17 | BIT16)
494 #define B_PCH_PCR_SPX_PCD_P4D BIT19 ///< Port 4 disable
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/ |
| H A D | PchRegsFia.h | 63 #define B_PCH_FIA_PCR_L4O (BIT19 | BIT18 | BIT17 | BIT16)
71 #define B_PCH_FIA_PCR_L12O (BIT19 | BIT18 | BIT17 | BIT16)
79 #define B_PCH_FIA_PCR_L20O (BIT19 | BIT18 | BIT17 | BIT16)
87 #define B_PCH_FIA_PCR_L28O (BIT19 | BIT18 | BIT17 | BIT16)
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| H A D | PchRegsHsio.h | 133 #define B_HSIO_PCR_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BI…
139 #define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BI…
148 #define B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BI…
160 #define B_HSIO_PCR_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BI…
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| H A D | PchRegsPmc.h | 141 #define B_ACPI_IO_SMI_STS_PATCH BIT19
372 #define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT19
414 #define B_PMC_PWRM_ETR3_SKIP_HOST_RST_HS BIT19
432 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_D2 BIT19
468 #define B_PMC_PWRM_CFG_SSMAW_MASK (BIT19 | BIT18) ///< SLP_SU…
469 #define V_PMC_PWRM_CFG_SSMAW_4S (BIT19 | BIT18) ///< 4 seco…
470 #define V_PMC_PWRM_CFG_SSMAW_1S BIT19 ///< 1 seco…
617 #define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_E1_FDIS_PMC BIT19 ///< PCIe Controller E Port 1 Fu…
643 #define B_PMC_PWRM_FUSE_DIS_RD_2_OTG_FUSE_SS_DIS BIT19 ///< OTG Fuse or Soft Strap Disab…
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| H A D | PchRegsPcie.h | 143 #define B_PCH_PCIE_CFG_MPC_UCEL (BIT20 | BIT19 | BIT18)
295 #define B_PCH_PCIE_CFG_PCIESTS1_LNKSTAT (BIT22 | BIT21 | BIT20 | BIT19)
401 #define B_PCH_PCIE_CFG_HAEQ_MACFOMC BIT19
431 #define B_PCH_PCIE_CFG_EQCFG2_PCET (BIT19 | BIT18 | BIT17 | BIT16)
461 #define B_SPX_PCR_PCD_P4D BIT19 ///< Port 4 disable
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| H A D | PchRegsSata.h | 152 #define B_SATA_CFG_MAP_SPD3 BIT19
169 #define B_SATA_CFG_PCS_P3P BIT19
316 #define B_SATA_MEM_AHCI_CAP_SNZO BIT19
363 #define B_SATA_MEM_AHCI_EM_CTRL_SUPP_SGPIO BIT19
487 #define B_SATA_MEM_AHCI_PxCMD_MPSP BIT19 ///< Mechanical Switch Attached to Port
571 #define B_SATA_MEM_AHCI_PXSERR_10B8B_DECERR BIT19
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| H A D | PchRegsGpio.h | 52 #define B_GPIO_PCR_MISCCFG_GPE0_DW2 (BIT19 | BIT18 | BIT17 | BIT16)
132 #define B_GPIO_PCR_RX_SCI_ROUTE BIT19
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| /dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| H A D | PchRegsLpss.h | 64 #define B_PCH_LPSS_DMAC_STSCMD_INTRSTS BIT19 // Interrupt Status
149 #define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status
236 #define B_PCH_LPSS_PWM_STSCMD_INTRSTS BIT19 // Interrupt Status
323 #define B_PCH_LPSS_HSUART_STSCMD_INTRSTS BIT19 // Interrupt Status
415 #define B_PCH_LPSS_SPI_STSCMD_INTRSTS BIT19 // Interrupt Status
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| H A D | PchRegsLpss.h | 58 #define B_PCH_LPSS_DMAC_STSCMD_INTRSTS BIT19 // Interrupt Status
143 #define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status
230 #define B_PCH_LPSS_PWM_STSCMD_INTRSTS BIT19 // Interrupt Status
317 #define B_PCH_LPSS_HSUART_STSCMD_INTRSTS BIT19 // Interrupt Status
409 #define B_PCH_LPSS_SPI_STSCMD_INTRSTS BIT19 // Interrupt Status
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/SimicsIch10Pkg/Include/Register/ |
| H A D | PchRegsPmc.h | 110 #define B_PCH_PMC_BM_CX_CNF_DPSN_BREAK_EN BIT19
122 #define B_PCH_PMC_ETR3_SKIP_HOST_RST_HS BIT19
218 #define B_PCH_SMI_STS_PATCH BIT19
422 #define B_PCH_PWRM_CFG_SSMAW_MASK (BIT19 | BIT18) ///< SLP_SU…
423 #define V_PCH_PWRM_CFG_SSMAW_4S (BIT19 | BIT18) ///< 4 seco…
424 #define V_PCH_PWRM_CFG_SSMAW_1S BIT19 ///< 1 seco…
597 #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E1_FUSE_DIS BIT19 ///< PCIe Controller E Port 1 Fus…
622 #define B_PCH_PWRM_FUSE_DIS_RD_2_OTG_FUSE_SS_DIS BIT19 ///< OTG Fuse or Soft Strap Disab…
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| /dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2TbltDevicePkg/Include/Guid/ |
| H A D | BoardFeatures.h | 62 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19)
67 #define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19
156 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)
161 #define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/ |
| H A D | BoardFeatures.h | 50 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19)
55 #define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19
144 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)
149 #define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/ |
| H A D | Bcm2836Sdio.h | 37 #define CCCE_ENABLE BIT19
62 #define WRITE_PROTECT_OFF BIT19
112 #define CIE_EN BIT19
128 #define CIE_SIGEN BIT19
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/TexasInstruments/Omap35xxPkg/PciEmulation/ |
| H A D | PciEmulation.c | 53 MmioAnd32 (GPIO5_BASE + GPIO_OE, ~BIT19); in ConfigureUSBHost()
54 MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19); in ConfigureUSBHost()
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/staging/rtl8723bs/include/ |
| H A D | hal_com_reg.h | 627 #define RRSR_MCS7 BIT19
777 #define IMR_BCNDOK2 BIT19 /* Beacon Queue DMA OK Interrupt 2 */
825 #define PHIMR_BCNDOK3 BIT19
851 #define PHIMR_BCNDOK7 BIT19
876 #define UHIMR_BCNDOK3 BIT19
902 #define UHIMR_BCNDOK7 BIT19
960 #define IMR_BCNDOK6_88E BIT19 /* Beacon Queue DMA OK Interrupt 6 */
1024 #define RCR_RSVD_BIT19 BIT19 /* Reserved */
1570 #define SDIO_HIMR_CPWM2_MSK BIT19
1596 #define SDIO_HISR_CPWM2 BIT19
[all …]
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/staging/rtl8723bs/include/ |
| H A D | hal_com_reg.h | 627 #define RRSR_MCS7 BIT19
777 #define IMR_BCNDOK2 BIT19 /* Beacon Queue DMA OK Interrupt 2 */
825 #define PHIMR_BCNDOK3 BIT19
851 #define PHIMR_BCNDOK7 BIT19
876 #define UHIMR_BCNDOK3 BIT19
902 #define UHIMR_BCNDOK7 BIT19
960 #define IMR_BCNDOK6_88E BIT19 /* Beacon Queue DMA OK Interrupt 6 */
1024 #define RCR_RSVD_BIT19 BIT19 /* Reserved */
1570 #define SDIO_HIMR_CPWM2_MSK BIT19
1596 #define SDIO_HISR_CPWM2 BIT19
[all …]
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/staging/rtl8723bs/include/ |
| H A D | hal_com_reg.h | 627 #define RRSR_MCS7 BIT19
777 #define IMR_BCNDOK2 BIT19 /* Beacon Queue DMA OK Interrupt 2 */
825 #define PHIMR_BCNDOK3 BIT19
851 #define PHIMR_BCNDOK7 BIT19
876 #define UHIMR_BCNDOK3 BIT19
902 #define UHIMR_BCNDOK7 BIT19
960 #define IMR_BCNDOK6_88E BIT19 /* Beacon Queue DMA OK Interrupt 6 */
1024 #define RCR_RSVD_BIT19 BIT19 /* Reserved */
1570 #define SDIO_HIMR_CPWM2_MSK BIT19
1596 #define SDIO_HISR_CPWM2 BIT19
[all …]
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/ |
| H A D | BcmGenetDxe.h | 59 #define SYS_REV_MINOR (BIT19|BIT18|BIT17|BIT16)
108 #define GENET_MDIO_REG (BIT20|BIT19|BIT18|BIT17|BIT16)
160 …_STATUS_BUFLEN (BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)
169 …_STATUS_BUFLEN (BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)
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