/dports/devel/vasm/vasm/cpus/ppc/ |
H A D | opcodes.h | 17 "twlgti", { RA, SI } ,{PPCCOM, OPTO(3,TOLGT)}, 19 "twllti", { RA, SI } ,{PPCCOM, OPTO(3,TOLLT)}, 21 "tweqi", { RA, SI } ,{PPCCOM, OPTO(3,TOEQ)}, 23 "twlgei", { RA, SI } ,{PPCCOM, OPTO(3,TOLGE)}, 31 "twgti", { RA, SI } ,{PPCCOM, OPTO(3,TOGT)}, 33 "twgei", { RA, SI } ,{PPCCOM, OPTO(3,TOGE)}, 45 "twi", { TO, RA, SI } ,{PPCCOM, OP(3)}, 588 "mulli", { RT, RA, SI } ,{PPCCOM, OP(7)}, 591 "subfic", { RT, RA, SI } ,{PPCCOM, OP(8)}, 606 "addic", { RT, RA, SI } ,{PPCCOM, OP(12)}, [all …]
|
/dports/editors/hte/ht-e9e63373148da5d7df397d8075740d8c096ecb1d/asm/ |
H A D | ppcopc.cc | 1207 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1208 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 1309 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 1555 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 1557 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 1567 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, 1573 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 1576 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } }, 2066 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 2265 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, [all …]
|
/dports/lang/smalltalk/smalltalk-3.2.5/opcode/ |
H A D | ppc-opc.c | 1300 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 1303 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 1306 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 1321 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, 1325 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, 1329 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 1331 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } }, 1334 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } }, 1787 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 1925 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, [all …]
|
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | ppc-opc.c | 1757 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1758 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 1854 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2347 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2350 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2370 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, 2374 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, 2378 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 2905 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3106 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, [all …]
|
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/ |
H A D | ppc-opc.c | 1776 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1777 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 1873 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2401 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2404 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2424 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, 2428 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, 2432 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 2959 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3160 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, [all …]
|
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | ppc-opc.c | 1757 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1758 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 1854 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2347 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2350 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2370 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, 2374 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, 2378 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 2905 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3106 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, [all …]
|
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/ |
H A D | ppc-opc.c | 1822 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1823 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 1921 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2449 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2452 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2472 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, 2476 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, 2480 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 3007 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3210 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, [all …]
|
/dports/devel/avr-gdb/gdb-7.3.1/opcodes/ |
H A D | ppc-opc.c | 1906 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 2640 {"li", OP(14), DRA_MASK, PPCCOM, PPCNONE, {RT, SI}}, 3178 {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCNONE, {0}}, 3386 {"nop", OP(24), 0xffffffff, PPCCOM, PPCNONE, {0}}, 3462 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, PPCNONE, {0}}, 5395 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, 5396 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, 5405 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, 5407 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, 5413 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, [all …]
|
/dports/devel/gdb761/gdb-7.6.1/opcodes/ |
H A D | ppc-opc.c | 2683 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 3433 {"li", OP(14), DRA_MASK, PPCCOM, PPCNONE, {RT, SI}}, 3971 {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCNONE, {0}}, 4179 {"nop", OP(24), 0xffffffff, PPCCOM, PPCNONE, {0}}, 4186 {"xnop", OP(26), 0xffffffff, PPCCOM, PPCNONE, {0}}, 6509 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, 6510 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, 6519 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, 6521 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, 6527 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, [all …]
|
/dports/emulators/qemu/qemu-6.2.0/disas/ |
H A D | ppc.c | 1956 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1957 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 2060 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2592 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2595 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2623 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 3150 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3360 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 4432 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, 5072 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, [all …]
|
/dports/emulators/qemu42/qemu-4.2.1/disas/ |
H A D | ppc.c | 1956 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1957 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 2060 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2592 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2595 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2623 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 3150 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3360 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 4432 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, 5072 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, [all …]
|
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/ |
H A D | ppc-dis.c | 1952 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1953 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 2053 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2581 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2584 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2612 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 3139 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3349 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 4412 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, 5050 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, [all …]
|
/dports/emulators/qemu5/qemu-5.2.0/disas/ |
H A D | ppc.c | 1956 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1957 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 2060 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2592 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2595 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2623 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 3150 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3360 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 4432 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, 5072 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, [all …]
|
/dports/emulators/qemu60/qemu-6.0.0/disas/ |
H A D | ppc.c | 1956 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1957 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 2060 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2592 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2595 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2623 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 3150 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3360 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 4432 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, 5072 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, [all …]
|
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/ |
H A D | ppc.c | 1953 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1954 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 2057 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2589 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2592 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2620 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 3147 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3357 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 4427 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, 5065 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, [all …]
|
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/ppc/gnu/ |
H A D | ppc-opc.c | 1834 #define PPCCOM (PPC_OPCODE_PPC | PPC_OPCODE_COMMON) macro 1835 #define NOPOWER4 (PPC_OPCODE_NOPOWER4 | PPCCOM) 1943 {"twi", OP(3), OP_MASK, PPCCOM, {TO, RA, SI}}, 2570 {"li", OP(14), DRA_MASK, PPCCOM, {RT, SI}}, 2575 {"la", OP(14), OP_MASK, PPCCOM, {RT, D, RA0}}, 3111 {"isync", XL(19,150), 0xffffffff, PPCCOM, {0}}, 3326 {"nop", OP(24), 0xffffffff, PPCCOM, {0}}, 3402 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, {0}}, 3403 {"tw", X(31,4), X_MASK, PPCCOM, {TO, RA, RB}}, 4392 {"sync", X(31,598), XSYNC_MASK, PPCCOM, {LS}}, [all …]
|
/dports/emulators/qemu-utils/qemu-4.2.1/disas/ |
H A D | ppc.c | 1956 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1957 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 2060 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2592 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2595 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2623 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 3150 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3360 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 4432 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, 5072 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, [all …]
|
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/ |
H A D | ppc.c | 1956 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1957 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 2060 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2592 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2595 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2623 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 3150 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3360 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 4432 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, 5072 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, [all …]
|
/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/ |
H A D | ppc.c | 1956 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1957 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 2060 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2592 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2595 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2623 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 3150 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3360 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 4432 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, 5072 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, [all …]
|
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/ |
H A D | ppc.c | 1956 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 1957 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 2060 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 2592 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2595 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2623 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 3150 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3360 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 4432 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, 5072 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, [all …]
|
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/ |
H A D | ppc-opc.c | 3004 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 4666 {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4673 {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4743 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}}, 4746 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, 7293 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, 7294 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, 7303 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, 7305 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, 7311 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, [all …]
|
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/ |
H A D | ppc-opc.c | 3004 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 4666 {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4673 {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4743 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}}, 4746 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, 7293 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, 7294 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, 7303 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, 7305 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, 7311 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, [all …]
|
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/powerpc/xmon/ |
H A D | ppc-opc.c | 2952 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 4612 {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4619 {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4689 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}}, 4692 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, 7243 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, 7244 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, 7253 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, 7255 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, 7261 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, [all …]
|
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/powerpc/xmon/ |
H A D | ppc-opc.c | 2952 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 4612 {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4619 {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4689 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}}, 4692 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, 7243 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, 7244 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, 7253 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, 7255 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, 7261 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, [all …]
|
/dports/multimedia/libv4l/linux-5.13-rc2/arch/powerpc/xmon/ |
H A D | ppc-opc.c | 2952 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON macro 4612 {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4619 {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4689 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}}, 4692 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, 7243 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, 7244 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, 7253 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, 7255 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, 7261 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, [all …]
|