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Searched refs:TCOBASE (Results 1 – 7 of 7) sorted by relevance

/dports/multimedia/libv4l/linux-5.13-rc2/drivers/watchdog/
H A DiTCO_wdt.c71 #define TCOBASE(p) ((p)->tco_res->start) macro
76 #define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
77 #define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
78 #define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
79 #define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
80 #define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
81 #define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
82 #define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
83 #define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
532 (u64)TCOBASE(p)); in iTCO_wdt_probe()
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/watchdog/
H A DiTCO_wdt.c71 #define TCOBASE(p) ((p)->tco_res->start) macro
76 #define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
77 #define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
78 #define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
79 #define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
80 #define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
81 #define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
82 #define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
83 #define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
532 (u64)TCOBASE(p)); in iTCO_wdt_probe()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/watchdog/
H A DiTCO_wdt.c71 #define TCOBASE(p) ((p)->tco_res->start) macro
76 #define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
77 #define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
78 #define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
79 #define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
80 #define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
81 #define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
82 #define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
83 #define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
532 (u64)TCOBASE(p)); in iTCO_wdt_probe()
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/i2c/busses/
H A Di2c-i801.c137 #define TCOBASE 0x050 macro
1609 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); in i801_add_tco()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/i2c/busses/
H A Di2c-i801.c137 #define TCOBASE 0x050 macro
1609 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); in i801_add_tco()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/i2c/busses/
H A Di2c-i801.c137 #define TCOBASE 0x050 macro
1609 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); in i801_add_tco()
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/AcpiTables/Dsdt/
H A DPch.asl265 // Define PCH TCOBASE I/O