Home
last modified time | relevance | path

Searched refs:ZRC (Results 1 – 25 of 57) sorted by relevance

123

/dports/biology/molden/molden5.8/plush/
H A DZRC1 mol="ZRC" Charge="-8"
/dports/editors/hte/ht-e9e63373148da5d7df397d8075740d8c096ecb1d/asm/
H A Dppcopc.cc1005 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
1011 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2939 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
2940 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
2945 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
2946 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
2948 { "drintx", ZRC(59,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
3065 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
3066 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
3077 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
[all …]
/dports/games/iortcw/iortcw-1.51c/MP/code/qcommon/
H A Dvm_powerpc_asm.c688 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
694 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
695 #define Z2_MASK ZRC (0x3f, 0xff, 1)
/dports/games/ioquake3/ioquake3-1.36/code/qcommon/
H A Dvm_powerpc_asm.c691 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
697 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
698 #define Z2_MASK ZRC (0x3f, 0xff, 1)
/dports/games/ioquake3-server/ioquake3-1.36/code/qcommon/
H A Dvm_powerpc_asm.c691 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
697 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
698 #define Z2_MASK ZRC (0x3f, 0xff, 1)
/dports/games/iortcw/iortcw-1.51c/SP/code/qcommon/
H A Dvm_powerpc_asm.c688 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
694 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
695 #define Z2_MASK ZRC (0x3f, 0xff, 1)
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/wan/
H A Dhdlc_ppp.c86 enum {INV = 0x10, IRC = 0x20, ZRC = 0x40, SCR = 0x80, SCA = 0x100, enumerator
290 { STA|0 , STA|1 ,STA|2, STA|3 ,STA|3, STA|3 ,ZRC|STA|2}, /* RTR */
324 if (action & ZRC) in ppp_cp_event()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/wan/
H A Dhdlc_ppp.c86 enum {INV = 0x10, IRC = 0x20, ZRC = 0x40, SCR = 0x80, SCA = 0x100, enumerator
290 { STA|0 , STA|1 ,STA|2, STA|3 ,STA|3, STA|3 ,ZRC|STA|2}, /* RTR */
324 if (action & ZRC) in ppp_cp_event()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/wan/
H A Dhdlc_ppp.c86 enum {INV = 0x10, IRC = 0x20, ZRC = 0x40, SCR = 0x80, SCA = 0x100, enumerator
290 { STA|0 , STA|1 ,STA|2, STA|3 ,STA|3, STA|3 ,ZRC|STA|2}, /* RTR */
324 if (action & ZRC) in ppp_cp_event()
/dports/games/openarena/openarena-engine-source-0.8.8/code/qcommon/
H A Dvm_powerpc_asm.c690 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
696 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
697 #define Z2_MASK ZRC (0x3f, 0xff, 1)
/dports/games/openarena-server/openarena-engine-source-0.8.8/code/qcommon/
H A Dvm_powerpc_asm.c690 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
696 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
697 #define Z2_MASK ZRC (0x3f, 0xff, 1)
/dports/emulators/qemu/qemu-6.2.0/disas/
H A Dppc.c1741 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
1747 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1748 #define Z2_MASK ZRC (0x3f, 0xff, 1)
4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
[all …]
/dports/emulators/qemu42/qemu-4.2.1/disas/
H A Dppc.c1741 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
1747 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1748 #define Z2_MASK ZRC (0x3f, 0xff, 1)
4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
[all …]
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/
H A Dppc-dis.c1740 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
1746 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1747 #define Z2_MASK ZRC (0x3f, 0xff, 1)
4749 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4750 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4755 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4756 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4921 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4922 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4933 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
[all …]
/dports/emulators/qemu5/qemu-5.2.0/disas/
H A Dppc.c1741 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
1747 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1748 #define Z2_MASK ZRC (0x3f, 0xff, 1)
4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
[all …]
/dports/emulators/qemu60/qemu-6.0.0/disas/
H A Dppc.c1741 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
1747 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1748 #define Z2_MASK ZRC (0x3f, 0xff, 1)
4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/
H A Dppc.c1741 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
1747 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1748 #define Z2_MASK ZRC (0x3f, 0xff, 1)
4764 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4765 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4770 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4771 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4936 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4937 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4948 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
[all …]
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/ppc/gnu/
H A Dppc-opc.c1585 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
1600 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1601 #define Z2_MASK ZRC (0x3f, 0xff, 1)
4832 {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, {FRT,FRA,FRB,RMC}},
4833 {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, {FRT,FRA,FRB,RMC}},
4874 {"dscli", ZRC(59,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}},
4875 {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}},
4877 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, {TE, FRT,FRB,RMC}},
4880 {"dscri", ZRC(59,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}},
4881 {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, {FRT, FRA, SH16}},
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/disas/
H A Dppc.c1741 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
1747 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1748 #define Z2_MASK ZRC (0x3f, 0xff, 1)
4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/
H A Dppc.c1741 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
1747 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1748 #define Z2_MASK ZRC (0x3f, 0xff, 1)
4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/
H A Dppc.c1741 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
1747 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1748 #define Z2_MASK ZRC (0x3f, 0xff, 1)
4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/
H A Dppc.c1741 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
1747 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1748 #define Z2_MASK ZRC (0x3f, 0xff, 1)
4769 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4770 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4775 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4776 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4941 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4942 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4953 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
[all …]
/dports/devel/avr-gdb/gdb-7.3.1/opcodes/
H A Dppc-opc.c1628 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
1665 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1666 #define Z2_MASK ZRC (0x3f, 0xff, 1)
4883 {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}},
4884 {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}},
4929 {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
4930 {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
4932 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}},
4935 {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
4936 {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}},
[all …]
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/
H A Dppc-opc.c2667 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
2722 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2723 #define Z2_MASK ZRC (0x3f, 0xff, 1)
5010 {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
5011 {"addex.", ZRC(31,170,1), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
6415 {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6416 {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6461 {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6462 {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6464 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
[all …]
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/
H A Dppc-opc.c2667 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) macro
2722 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2723 #define Z2_MASK ZRC (0x3f, 0xff, 1)
5010 {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
5011 {"addex.", ZRC(31,170,1), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
6415 {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6416 {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6461 {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6462 {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6464 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
[all …]

123