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Searched refs:getKillRegState (Results 1 – 25 of 41) sorted by relevance

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/minix/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp47 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
50 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
53 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
56 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
59 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
62 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp297 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
300 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
304 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
315 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
369 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
372 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
375 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
378 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
383 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
/minix/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrBuilder.h110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp55 .addReg(SrcReg, getKillRegState(KillSrc))); in copyPhysReg()
65 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
94 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
H A DMLxExpansionPass.cpp294 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
295 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction()
305 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
306 .addReg(AccReg, getKillRegState(AccKill)); in ExpandFPMLxInstruction()
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
H A DARMLoadStoreOptimizer.cpp579 .addReg(Base, getKillRegState(BaseKill)); in MergeOps()
582 .addReg(Base, getKillRegState(BaseKill)) in MergeOps()
631 .addReg(Base, getKillRegState(BaseKill)); in MergeOps()
641 MIB.addReg(Base, getKillRegState(BaseKill)); in MergeOps()
648 | getKillRegState(Regs[i].second)); in MergeOps()
1157 .addReg(Base, getKillRegState(BaseKill)) in MergeBaseUpdateLSMultiple()
1317 getKillRegState(MO.isKill()))); in MergeBaseUpdateLoadStore()
1348 .addReg(MO.getReg(), getKillRegState(MO.isKill())) in MergeBaseUpdateLoadStore()
1354 .addReg(MO.getReg(), getKillRegState(MO.isKill())) in MergeBaseUpdateLoadStore()
1500 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
[all …]
H A DARMBaseInstrInfo.cpp729 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyToCPSR()
766 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
768 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
900 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
904 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
912 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
940 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
944 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
957 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
978 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
[all …]
H A DThumb2InstrInfo.cpp122 .addReg(SrcReg, getKillRegState(KillSrc))); in copyPhysReg()
145 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
158 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1741 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr()
1745 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr()
1767 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr()
1768 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rrr()
1772 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr()
1773 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rrr()
1791 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_ri()
1795 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_ri()
1814 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rii()
1819 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rii()
[all …]
/minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp1601 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
1611 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
1679 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
1683 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
1704 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
1707 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
1775 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
1781 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
1788 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
1794 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
[all …]
H A DAArch64AdvSIMDScalarPass.cpp276 .addReg(Src, getKillRegState(IsKill)); in insertCopy()
346 .addReg(Src0, getKillRegState(true), SubReg0) in transformInstruction()
347 .addReg(Src1, getKillRegState(true), SubReg1); in transformInstruction()
H A DAArch64FastISel.cpp385 .addReg(TmpReg, getKillRegState(true)); in materializeFP()
1259 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rr()
1303 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_ri()
1340 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rs()
1341 .addReg(RHSReg, getKillRegState(RHSIsKill)) in emitAddSub_rs()
1380 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rx()
2501 .addReg(TmpReg1, getKillRegState(true)) in selectCmp()
2918 .addReg(DstReg, getKillRegState(true)); in fastLowerArguments()
4040 .addReg(Op0, getKillRegState(Op0IsKill)); in emitLSR_ri()
4161 .addReg(Op0, getKillRegState(Op0IsKill)); in emitASR_ri()
[all …]
/minix/external/bsd/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
148 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
191 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
H A DXCoreInstrInfo.cpp350 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
362 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
386 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/minix/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp56 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
60 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
104 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp610 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()
611 .addReg(cmpOp2, getKillRegState(MO2IsKill)) in runOnMachineFunction()
621 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()
627 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()
H A DHexagonCopyToCombine.cpp609 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill()); in emitCombineIR()
633 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill()); in emitCombineRI()
659 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill()); in emitCombineRR()
660 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill()); in emitCombineRR()
H A DHexagonInstrInfo.cpp458 addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
464 addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
493 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
497 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
501 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) in copyPhysReg()
173 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
218 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStack()
474 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); in expandPseudoMTLoHi()
475 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); in expandPseudoMTLoHi()
495 unsigned KillSrc = getKillRegState(Src.isKill()); in expandCvtFPInt()
H A DMipsSEFrameLowering.cpp179 .addReg(Src, getKillRegState(I->getOperand(0).isKill())); in expandStoreCCond()
231 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill()); in expandStoreACC()
267 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill()); in expandCopyACC()
H A DMips16InstrInfo.cpp90 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
106 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)). in storeRegToStack()
/minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp282 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstruction()
283 .addReg(Reg1, getKillRegState(Reg1IsKill)) in commuteInstruction()
773 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
794 getKillRegState(isKill)), in StoreRegToStackSlot()
800 getKillRegState(isKill)), in StoreRegToStackSlot()
805 getKillRegState(isKill)), in StoreRegToStackSlot()
810 getKillRegState(isKill)), in StoreRegToStackSlot()
815 getKillRegState(isKill)), in StoreRegToStackSlot()
821 getKillRegState(isKill)), in StoreRegToStackSlot()
827 getKillRegState(isKill)), in StoreRegToStackSlot()
[all …]
H A DPPCRegisterInfo.cpp375 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in lowerDynamicAlloc()
383 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); in lowerDynamicAlloc()
400 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in lowerDynamicAlloc()
408 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); in lowerDynamicAlloc()
446 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); in lowerCRSpilling()
562 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); in lowerCRBitSpilling()
648 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); in lowerVRSAVESpilling()
H A DPPCFrameLowering.cpp679 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
1055 .addReg(TempReg, getKillRegState(i == e-1)); in emitEpilogue()
1503 getKillRegState(true)), in spillCalleeSavedRegisters()
1541 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); in restoreCRs()
1545 .addReg(MoveReg, getKillRegState(!CR4Spilled))); in restoreCRs()
1549 .addReg(MoveReg, getKillRegState(true))); in restoreCRs()
/minix/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp178 .addReg(SrcReg, getKillRegState(KillSrc)); in emitGRX32Move()
184 .addReg(SrcReg, getKillRegState(KillSrc)) in emitGRX32Move()
585 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
602 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx); in storeRegToStackSlot()
710 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg()); in convertToThreeAddress()
738 .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg()) in convertToThreeAddress()

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