/dports/devel/arduino-core/Arduino-b439a77/hardware/arduino/sam/system/CMSIS/CMSIS/Include/ |
H A D | core_cm3.h | 798 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 799 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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H A D | core_cm4.h | 926 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 927 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f37x/ |
H A D | core_sc300.h | 1072 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1073 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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H A D | core_cm3.h | 1101 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1102 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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H A D | core_cm4.h | 1234 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1235 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/ |
H A D | core_sc300.h | 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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H A D | core_cm3.h | 1245 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1246 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f30x/ |
H A D | core_cm3.h | 1198 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1199 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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H A D | core_sc300.h | 1178 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1179 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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H A D | core_cm4.h | 1344 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1345 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f4xx/ |
H A D | core_cm3.h | 1198 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1199 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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H A D | core_sc300.h | 1178 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1179 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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H A D | core_cm4.h | 1344 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1345 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/ |
H A D | core_sc300.h | 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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H A D | core_cm3.h | 1245 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1246 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/ |
H A D | core_sc300.h | 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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H A D | core_cm3.h | 1245 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… in decompress() 1246 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core… in decompress()
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/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/ |
H A D | core_sc300.h | 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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H A D | core_cm3.h | 1245 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1246 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f37x/ |
H A D | core_cm4.h | 1234 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1235 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_g4xx/ |
H A D | core_cm4.h | 1344 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1345 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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/dports/devel/tinygo/tinygo-0.14.1/lib/CMSIS/CMSIS/Include/ |
H A D | core_sc300.h | 1263 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core… macro 1264 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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H A D | core_cm3.h | 1281 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core… macro 1282 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f4xx/ |
H A D | core_cm4.h | 1344 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< Core… macro 1345 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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/dports/lang/micropython/micropython-1.17/lib/cmsis/inc/ |
H A D | core_armv8mbl.h | 1037 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core… macro 1038 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core…
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