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Searched refs:REG_SET (Results 1 – 25 of 36) sorted by relevance

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/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_hubp.c317 REG_SET(DCSURF_FLIP_CONTROL, 0, in hubp1_program_surface_flip_and_addr()
543 REG_SET(BLANK_OFFSET_1, 0, in hubp1_program_deadline()
546 REG_SET(DST_DIMENSIONS, 0, in hubp1_program_deadline()
577 REG_SET(NOM_PARAMETERS_0, 0, in hubp1_program_deadline()
581 REG_SET(NOM_PARAMETERS_1, 0, in hubp1_program_deadline()
584 REG_SET(NOM_PARAMETERS_4, 0, in hubp1_program_deadline()
587 REG_SET(NOM_PARAMETERS_5, 0, in hubp1_program_deadline()
612 REG_SET(NOM_PARAMETERS_2, 0, in hubp1_program_deadline()
616 REG_SET(NOM_PARAMETERS_3, 0, in hubp1_program_deadline()
619 REG_SET(NOM_PARAMETERS_6, 0, in hubp1_program_deadline()
[all …]
H A Ddcn10_dpp_cm.c131 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
185 REG_SET( in program_gamut_remap()
232 REG_SET(CM_TEST_DEBUG_INDEX, 0, in dpp1_cm_program_color_matrix()
354 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp1_cm_power_on_regamma_lut()
487 REG_SET(CM_TEST_DEBUG_INDEX, 0, in dpp1_program_input_csc()
520 REG_SET(CM_ICSC_CONTROL, 0, in dpp1_program_input_csc()
608 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp1_power_on_degamma_lut()
701 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp1_program_degamma_lut()
703 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp1_program_degamma_lut()
705 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp1_program_degamma_lut()
[all …]
H A Ddcn10_mpc.c54 REG_SET(MPCC_BG_R_CR[mpcc_id], 0, in mpc1_set_bg_color()
56 REG_SET(MPCC_BG_G_Y[mpcc_id], 0, in mpc1_set_bg_color()
58 REG_SET(MPCC_BG_B_CB[mpcc_id], 0, in mpc1_set_bg_color()
213 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_insert_plane()
297 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, in mpc1_remove_mpcc()
301 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, in mpc1_remove_mpcc()
311 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); in mpc1_remove_mpcc()
312 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_remove_mpcc()
313 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf); in mpc1_remove_mpcc()
321 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf); in mpc1_remove_mpcc()
[all …]
H A Ddcn10_optc.c72 REG_SET(OTG_VSTARTUP_PARAM, 0, in optc1_program_global_sync()
79 REG_SET(OTG_VREADY_PARAM, 0, in optc1_program_global_sync()
87 REG_SET(OTG_STEREO_CONTROL, 0, in optc1_disable_stereo()
203 REG_SET(OTG_H_TOTAL, 0, in optc1_program_timing()
250 REG_SET(OTG_V_TOTAL, 0, in optc1_program_timing()
256 REG_SET(OTG_V_TOTAL_MAX, 0, in optc1_program_timing()
258 REG_SET(OTG_V_TOTAL_MIN, 0, in optc1_program_timing()
845 REG_SET(OTG_V_TOTAL_MAX, 0, in optc1_set_drr()
848 REG_SET(OTG_V_TOTAL_MIN, 0, in optc1_set_drr()
864 REG_SET(OTG_V_TOTAL_MIN, 0, in optc1_set_drr()
[all …]
H A Ddcn10_cm_common.c83 REG_SET(reg->start_slope_cntl_b, 0, in cm_helper_program_xfer_func()
85 REG_SET(reg->start_slope_cntl_g, 0, in cm_helper_program_xfer_func()
87 REG_SET(reg->start_slope_cntl_r, 0, in cm_helper_program_xfer_func()
90 REG_SET(reg->start_end_cntl1_b, 0, in cm_helper_program_xfer_func()
96 REG_SET(reg->start_end_cntl1_g, 0, in cm_helper_program_xfer_func()
102 REG_SET(reg->start_end_cntl1_r, 0, in cm_helper_program_xfer_func()
H A Ddcn10_opp.c96 REG_SET(FMT_DITHER_RAND_R_SEED, 0, in opp1_set_spatial_dither()
99 REG_SET(FMT_DITHER_RAND_G_SEED, 0, in opp1_set_spatial_dither()
102 REG_SET(FMT_DITHER_RAND_B_SEED, 0, in opp1_set_spatial_dither()
H A Ddcn10_dpp_dscl.c584 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in dpp1_dscl_set_manual_ratio_init()
587 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in dpp1_dscl_set_manual_ratio_init()
590 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0, in dpp1_dscl_set_manual_ratio_init()
593 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0, in dpp1_dscl_set_manual_ratio_init()
H A Ddcn10_dpp.c129 REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
262 REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode); in dpp1_cm_set_regamma_pwl()
397 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp1_cnv_setup()
H A Ddcn10_stream_encoder.c410 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); in enc1_stream_encoder_dp_set_stream_attribute()
1174 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); in enc1_se_audio_setup()
1271 REG_SET(DP_SEC_AUD_N, 0, in enc1_se_setup_dp_audio()
1275 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, in enc1_se_setup_dp_audio()
H A Ddcn10_hw_sequencer.c522 REG_SET(DC_IP_REQUEST_CNTL, 0, in power_on_plane()
526 REG_SET(DC_IP_REQUEST_CNTL, 0, in power_on_plane()
543 REG_SET(DC_IP_REQUEST_CNTL, 0, in undo_DEGVIDCN10_253_wa()
547 REG_SET(DC_IP_REQUEST_CNTL, 0, in undo_DEGVIDCN10_253_wa()
572 REG_SET(DC_IP_REQUEST_CNTL, 0, in apply_DEGVIDCN10_253_wa()
576 REG_SET(DC_IP_REQUEST_CNTL, 0, in apply_DEGVIDCN10_253_wa()
895 REG_SET(DC_IP_REQUEST_CNTL, 0, in plane_atomic_power_down()
900 REG_SET(DC_IP_REQUEST_CNTL, 0, in plane_atomic_power_down()
/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_ipp.c127 REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, in dce_ipp_cursor_set_attributes()
130 REG_SET(CUR_SURFACE_ADDRESS, 0, in dce_ipp_cursor_set_attributes()
178 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); in dce_ipp_program_input_lut()
181 REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); in dce_ipp_program_input_lut()
193 REG_SET(DC_LUT_RW_INDEX, 0, in dce_ipp_program_input_lut()
197 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
200 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
203 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
210 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); in dce_ipp_program_input_lut()
H A Ddce_transform.c1004 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1009 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1016 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1021 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1027 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1044 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1050 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1056 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1062 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
1071 REG_SET(OUTPUT_CSC_CONTROL, 0, in configure_graphics_mode()
[all …]
H A Ddce_mem_input.c413 REG_SET(GRPH_X_START, 0, in program_size_and_rotation()
416 REG_SET(GRPH_Y_START, 0, in program_size_and_rotation()
419 REG_SET(GRPH_X_END, 0, in program_size_and_rotation()
422 REG_SET(GRPH_Y_END, 0, in program_size_and_rotation()
425 REG_SET(GRPH_PITCH, 0, in program_size_and_rotation()
428 REG_SET(HW_ROTATION, 0, in program_size_and_rotation()
594 REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control, in dce_mi_allocate_dmif()
631 REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control, in dce_mi_free_dmif()
653 REG_SET(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0, in program_sec_addr()
667 REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in program_pri_addr()
[all …]
H A Ddce_audio.c62 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, in write_indirect_azalia_reg()
66 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0, in write_indirect_azalia_reg()
80 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, in read_indirect_azalia_reg()
H A Ddce_aux.c226 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
230 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
243 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
H A Ddce_stream_encoder.c446 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); in dce110_stream_encoder_dp_set_stream_attribute()
1313 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); in dce110_se_audio_setup()
1413 REG_SET(DP_SEC_AUD_N, 0, in dce110_se_setup_dp_audio()
1417 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, in dce110_se_setup_dp_audio()
/dragonfly/sys/dev/drm/amd/display/dc/gpio/
H A Dhw_ddc.c113 REG_SET(gpio.MASK_reg, regval, in set_config()
122 REG_SET(gpio.MASK_reg, regval, in set_config()
151 REG_SET(gpio.MASK_reg, regval, in set_config()
/dragonfly/sys/dev/drm/radeon/
H A Dr300d.h61 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
62 REG_SET(PACKET0_COUNT, (n)))
63 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
65 REG_SET(PACKET3_IT_OPCODE, (op)) | \
66 REG_SET(PACKET3_COUNT, (n)))
H A Drv515d.h201 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
202 REG_SET(PACKET0_COUNT, (n)))
203 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
205 REG_SET(PACKET3_IT_OPCODE, (op)) | \
206 REG_SET(PACKET3_COUNT, (n)))
H A Dr100d.h60 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
61 REG_SET(PACKET0_COUNT, (n)))
62 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
64 REG_SET(PACKET3_IT_OPCODE, (op)) | \
65 REG_SET(PACKET3_COUNT, (n)))
H A Drs400.c147 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); in rs400_gart_enable()
148 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); in rs400_gart_enable()
/dragonfly/sys/dev/drm/amd/display/dc/i2caux/dce110/
H A Daux_engine_dce110.c249 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
253 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
265 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
/dragonfly/sys/dev/drm/amd/display/dc/inc/
H A Dreg_helper.h45 #ifdef REG_SET
46 #undef REG_SET
63 #define REG_SET(reg_name, initial_val, field, val) \ macro
385 REG_SET(reg, val, field, value2); }
390 REG_SET(reg, val, f2, v2); }
394 val = REG_SET(reg, val, f2, v2); \
395 REG_SET(reg, val, f3, v3); }
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsoc15d.h48 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
H A Dvid.h105 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

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