/dragonfly/sys/dev/drm/radeon/ |
H A D | radeon_cursor.c | 49 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor() 56 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor() 66 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, in radeon_hide_cursor() 70 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, in radeon_hide_cursor() 115 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in radeon_show_cursor() 122 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, in radeon_show_cursor() 218 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, in radeon_cursor_move_locked() 223 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, in radeon_cursor_move_locked() 232 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset, in radeon_cursor_move_locked() 236 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, in radeon_cursor_move_locked() [all …]
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H A D | radeon_display.c | 49 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut() 122 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut() 125 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut() 127 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut() 129 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut() 157 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut() 162 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut() 165 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut() 168 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut() 172 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut() [all …]
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H A D | atombios_crtc.c | 1423 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base() 1430 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base() 1437 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base() 1606 radeon_crtc->crtc_offset, (u32) fb_location); in avivo_crtc_do_set_base() 1612 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base() 1620 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base() 1621 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base() 1627 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in avivo_crtc_do_set_base() 2169 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); in atombios_crtc_disable() 2252 radeon_crtc->crtc_offset = in radeon_atombios_init_crtc() [all …]
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H A D | radeon_legacy_crtc.c | 41 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup() 42 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup() 43 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup() 382 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; in radeon_crtc_do_set_base() local 546 crtc_offset = (u32)base; in radeon_crtc_do_set_base() 556 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); in radeon_crtc_do_set_base() 557 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); in radeon_crtc_do_set_base() 558 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); in radeon_crtc_do_set_base() 728 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); in radeon_set_crtc_timing() 730 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); in radeon_set_crtc_timing() [all …]
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H A D | rs600.c | 115 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip() 120 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip() 123 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rs600_page_flip() 125 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip() 127 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip() 140 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip() 148 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending() 321 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_prepare() 323 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in rs600_pm_prepare() 339 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_finish() [all …]
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H A D | rv515.c | 708 int index_reg = 0x6578 + crtc->crtc_offset; in atom_rv515_force_tv_scaler() 709 int data_reg = 0x657c + crtc->crtc_offset; in atom_rv515_force_tv_scaler() 711 WREG32(0x659C + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler() 712 WREG32(0x6594 + crtc->crtc_offset, 0x705); in atom_rv515_force_tv_scaler() 713 WREG32(0x65A4 + crtc->crtc_offset, 0x10001); in atom_rv515_force_tv_scaler() 714 WREG32(0x65D8 + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler() 715 WREG32(0x65B0 + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler() 716 WREG32(0x65C0 + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler() 717 WREG32(0x65D4 + crtc->crtc_offset, 0x0); in atom_rv515_force_tv_scaler()
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H A D | rv770.c | 804 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rv770_page_flip() 809 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip() 812 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rv770_page_flip() 821 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip() 823 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip() 828 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rv770_page_flip() 836 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip() 844 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rv770_page_flip_pending()
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H A D | evergreen.c | 1330 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt() 1406 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in evergreen_page_flip() 1410 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in evergreen_page_flip() 1429 return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & in evergreen_page_flip_pending() 1664 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_prepare() 1666 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_prepare() 1689 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_finish() 1691 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_finish() 1849 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); in evergreen_line_buffer_adjust() 2286 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); in evergreen_program_watermarks() [all …]
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H A D | atombios_encoders.c | 2140 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, in atombios_apply_encoder_quirks() 2143 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); in atombios_apply_encoder_quirks() 2146 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, in atombios_apply_encoder_quirks() 2149 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); in atombios_apply_encoder_quirks() 2152 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, in atombios_apply_encoder_quirks() 2155 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); in atombios_apply_encoder_quirks()
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H A D | si.c | 1990 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, in dce6_line_buffer_adjust() 2421 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); in dce6_program_watermarks() 2425 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks() 2426 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks() 2430 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); in dce6_program_watermarks() 2433 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks() 2434 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks() 2438 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); in dce6_program_watermarks() 2441 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); in dce6_program_watermarks() 2442 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); in dce6_program_watermarks()
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H A D | cik.c | 8770 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt() 8820 WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset, in dce8_line_buffer_adjust() 9318 wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset); in dce8_program_watermarks() 9322 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_watermarks() 9323 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce8_program_watermarks() 9327 tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset); in dce8_program_watermarks() 9330 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_watermarks() 9331 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce8_program_watermarks() 9335 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask); in dce8_program_watermarks()
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H A D | radeon_mode.h | 335 uint32_t crtc_offset; member
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H A D | r100.c | 164 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip() 168 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip() 176 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip() 194 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
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H A D | r600.c | 336 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | dce_v10_0.c | 1816 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); in dce_v10_0_grph_enable() 1818 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_grph_enable() 2032 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base() 2036 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base() 2317 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v10_0_cursor_move_locked() 2676 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; in dce_v10_0_crtc_init() 2679 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; in dce_v10_0_crtc_init() 2682 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; in dce_v10_0_crtc_init() 2685 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; in dce_v10_0_crtc_init() 2688 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; in dce_v10_0_crtc_init() [all …]
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H A D | dce_v11_0.c | 1858 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); in dce_v11_0_grph_enable() 1860 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_grph_enable() 2074 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base() 2078 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base() 2396 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v11_0_cursor_move_locked() 2784 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; in dce_v11_0_crtc_init() 2787 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; in dce_v11_0_crtc_init() 2790 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; in dce_v11_0_crtc_init() 2793 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; in dce_v11_0_crtc_init() 2796 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; in dce_v11_0_crtc_init() [all …]
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H A D | amdgpu_mode.h | 393 uint32_t crtc_offset; member
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