/dragonfly/sys/dev/drm/include/drm/ |
H A D | drm_atomic.h | 239 struct __drm_crtcs_state *crtcs; member 370 return state->crtcs[drm_crtc_index(crtc)].state; in drm_atomic_get_existing_crtc_state() 385 return state->crtcs[drm_crtc_index(crtc)].old_state; in drm_atomic_get_old_crtc_state() 399 return state->crtcs[drm_crtc_index(crtc)].new_state; in drm_atomic_get_new_crtc_state() 660 for_each_if ((__state)->crtcs[__i].ptr && \ 661 ((crtc) = (__state)->crtcs[__i].ptr, \ 662 (old_crtc_state) = (__state)->crtcs[__i].old_state, \ 680 for_each_if ((__state)->crtcs[__i].ptr && \ 681 ((crtc) = (__state)->crtcs[__i].ptr, \ 699 for_each_if ((__state)->crtcs[__i].ptr && \ [all …]
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H A D | drm_lease.h | 39 drm_lease_filter_crtcs(struct drm_file *file_priv, uint32_t crtcs) in drm_lease_filter_crtcs() argument 41 return crtcs; in drm_lease_filter_crtcs()
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H A D | drm_fb_helper.h | 122 struct drm_fb_helper_crtc **crtcs,
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | dce_virtual.c | 247 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_virtual_crtc_init() 424 memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS); in dce_virtual_sw_fini() 484 if (adev->mode_info.crtcs[i]) in dce_virtual_hw_fini() 663 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_virtual_pageflip() 725 if (state && !adev->mode_info.crtcs[crtc]->vsync_timer_enabled) { in dce_virtual_set_crtc_vblank_interrupt_state() 727 hrtimer_init(&adev->mode_info.crtcs[crtc]->vblank_timer, in dce_virtual_set_crtc_vblank_interrupt_state() 729 hrtimer_set_expires(&adev->mode_info.crtcs[crtc]->vblank_timer, in dce_virtual_set_crtc_vblank_interrupt_state() 731 adev->mode_info.crtcs[crtc]->vblank_timer.function = in dce_virtual_set_crtc_vblank_interrupt_state() 733 hrtimer_start(&adev->mode_info.crtcs[crtc]->vblank_timer, in dce_virtual_set_crtc_vblank_interrupt_state() 737 hrtimer_cancel(&adev->mode_info.crtcs[crtc]->vblank_timer); in dce_virtual_set_crtc_vblank_interrupt_state() [all …]
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H A D | dce_v10_0.c | 234 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_page_flip() 1153 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v10_0_bandwidth_update() 1157 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v10_0_bandwidth_update() 1158 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v10_0_bandwidth_update() 1159 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v10_0_bandwidth_update() 2543 if (adev->mode_info.crtcs[i] && in dce_v10_0_crtc_disable() 2544 adev->mode_info.crtcs[i]->enabled && in dce_v10_0_crtc_disable() 2546 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v10_0_crtc_disable() 2666 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v10_0_crtc_init() 3102 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_pageflip_irq()
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H A D | dce_v11_0.c | 252 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v11_0_page_flip() 1179 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v11_0_bandwidth_update() 1183 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v11_0_bandwidth_update() 1184 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v11_0_bandwidth_update() 1185 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v11_0_bandwidth_update() 2622 if (adev->mode_info.crtcs[i] && in dce_v11_0_crtc_disable() 2623 adev->mode_info.crtcs[i]->enabled && in dce_v11_0_crtc_disable() 2625 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v11_0_crtc_disable() 2774 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v11_0_crtc_init() 3228 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v11_0_pageflip_irq()
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H A D | atombios_crtc.c | 263 if (adev->mode_info.crtcs[i] && in amdgpu_atombios_crtc_program_ss() 264 adev->mode_info.crtcs[i]->enabled && in amdgpu_atombios_crtc_program_ss() 266 pll_id == adev->mode_info.crtcs[i]->pll_id) { in amdgpu_atombios_crtc_program_ss()
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H A D | amdgpu_display.c | 76 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; in amdgpu_display_flip_work_func() 835 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; in amdgpu_display_get_crtc_scanoutpos()
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H A D | amdgpu_kms.c | 282 crtc = (struct drm_crtc *)minfo->crtcs[i]; in amdgpu_info_ioctl() 1010 if (adev->mode_info.crtcs[pipe]) { in amdgpu_get_vblank_counter_kms() 1023 &adev->mode_info.crtcs[pipe]->base.hwmode); in amdgpu_get_vblank_counter_kms()
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H A D | amdgpu_mode.h | 327 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; member
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/dragonfly/sys/dev/drm/radeon/ |
H A D | rs690.c | 251 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in rs690_line_buffer_adjust() 254 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in rs690_line_buffer_adjust() 598 if (rdev->mode_info.crtcs[0]->base.enabled) in rs690_bandwidth_update() 599 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs690_bandwidth_update() 600 if (rdev->mode_info.crtcs[1]->base.enabled) in rs690_bandwidth_update() 601 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs690_bandwidth_update() 625 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); in rs690_bandwidth_update() 626 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); in rs690_bandwidth_update() 628 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true); in rs690_bandwidth_update() 629 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true); in rs690_bandwidth_update()
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H A D | rv515.c | 1239 if (rdev->mode_info.crtcs[0]->base.enabled) in rv515_bandwidth_avivo_update() 1240 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_avivo_update() 1241 if (rdev->mode_info.crtcs[1]->base.enabled) in rv515_bandwidth_avivo_update() 1242 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rv515_bandwidth_avivo_update() 1245 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); in rv515_bandwidth_avivo_update() 1248 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); in rv515_bandwidth_avivo_update() 1249 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); in rv515_bandwidth_avivo_update() 1281 if (rdev->mode_info.crtcs[0]->base.enabled) in rv515_bandwidth_update() 1282 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_update() 1283 if (rdev->mode_info.crtcs[1]->base.enabled) in rv515_bandwidth_update() [all …]
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H A D | rs600.c | 114 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip() 145 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip_pending() 899 if (rdev->mode_info.crtcs[0]->base.enabled) in rs600_bandwidth_update() 900 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs600_bandwidth_update() 901 if (rdev->mode_info.crtcs[1]->base.enabled) in rs600_bandwidth_update() 902 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs600_bandwidth_update()
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H A D | radeon_display.c | 276 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_vblank() 332 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && in radeon_crtc_handle_vblank() 357 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_flip() 404 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; in radeon_flip_work_func() 682 rdev->mode_info.crtcs[index] = radeon_crtc; in radeon_crtc_init() 1969 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; in radeon_get_crtc_scanoutpos()
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H A D | radeon_kms.c | 302 crtc = (struct drm_crtc *)minfo->crtcs[i]; in radeon_info_ioctl() 814 if (rdev->mode_info.crtcs[pipe]) { in radeon_get_vblank_counter_kms() 827 &rdev->mode_info.crtcs[pipe]->base.hwmode); in radeon_get_vblank_counter_kms()
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H A D | atombios_crtc.c | 463 if (rdev->mode_info.crtcs[i] && in atombios_crtc_program_ss() 464 rdev->mode_info.crtcs[i]->enabled && in atombios_crtc_program_ss() 466 pll_id == rdev->mode_info.crtcs[i]->pll_id) { in atombios_crtc_program_ss() 2175 if (rdev->mode_info.crtcs[i] && in atombios_crtc_disable() 2176 rdev->mode_info.crtcs[i]->enabled && in atombios_crtc_disable() 2178 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { in atombios_crtc_disable()
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H A D | r100.c | 158 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip() 191 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip_pending() 3237 if (rdev->mode_info.crtcs[0]->base.enabled) { in r100_bandwidth_update() 3239 rdev->mode_info.crtcs[0]->base.primary->fb; in r100_bandwidth_update() 3241 mode1 = &rdev->mode_info.crtcs[0]->base.mode; in r100_bandwidth_update() 3245 if (rdev->mode_info.crtcs[1]->base.enabled) { in r100_bandwidth_update() 3247 rdev->mode_info.crtcs[1]->base.primary->fb; in r100_bandwidth_update() 3249 mode2 = &rdev->mode_info.crtcs[1]->base.mode; in r100_bandwidth_update() 3655 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in r100_bandwidth_update() 3658 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in r100_bandwidth_update()
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H A D | evergreen.c | 1403 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip() 1426 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip_pending() 2316 if (rdev->mode_info.crtcs[i]->base.enabled) in evergreen_bandwidth_update() 2320 mode0 = &rdev->mode_info.crtcs[i]->base.mode; in evergreen_bandwidth_update() 2321 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; in evergreen_bandwidth_update() 2322 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); in evergreen_bandwidth_update() 2323 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); in evergreen_bandwidth_update() 2324 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); in evergreen_bandwidth_update() 2325 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); in evergreen_bandwidth_update()
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H A D | rv770.c | 803 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rv770_page_flip() 841 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rv770_page_flip_pending()
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H A D | si.c | 2463 if (rdev->mode_info.crtcs[i]->base.enabled) in dce6_bandwidth_update() 2467 mode0 = &rdev->mode_info.crtcs[i]->base.mode; in dce6_bandwidth_update() 2468 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; in dce6_bandwidth_update() 2469 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); in dce6_bandwidth_update() 2470 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); in dce6_bandwidth_update() 2471 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); in dce6_bandwidth_update() 2472 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); in dce6_bandwidth_update()
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/dragonfly/sys/dev/drm/ |
H A D | drm_atomic.c | 57 kfree(state->crtcs); in drm_atomic_state_default_release() 82 sizeof(*state->crtcs), GFP_KERNEL); in drm_atomic_state_init() 83 if (!state->crtcs) in drm_atomic_state_init() 158 struct drm_crtc *crtc = state->crtcs[i].ptr; in drm_atomic_state_default_clear() 164 state->crtcs[i].state); in drm_atomic_state_default_clear() 166 state->crtcs[i].ptr = NULL; in drm_atomic_state_default_clear() 167 state->crtcs[i].state = NULL; in drm_atomic_state_default_clear() 286 state->crtcs[index].state = crtc_state; in drm_atomic_get_crtc_state() 287 state->crtcs[index].old_state = crtc->state; in drm_atomic_get_crtc_state() 288 state->crtcs[index].new_state = crtc_state; in drm_atomic_get_crtc_state() [all …]
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H A D | drm_fb_helper.c | 2313 struct drm_fb_helper_crtc **crtcs, *crtc; in drm_pick_crtcs() local 2327 crtcs = kcalloc(fb_helper->connector_count, in drm_pick_crtcs() 2329 if (!crtcs) in drm_pick_crtcs() 2379 crtcs[n] = crtc; in drm_pick_crtcs() 2385 memcpy(best_crtcs, crtcs, in drm_pick_crtcs() 2391 kfree(crtcs); in drm_pick_crtcs() 2399 struct drm_fb_helper_crtc **crtcs; in drm_setup_crtcs() local 2409 crtcs = kcalloc(fb_helper->connector_count, in drm_setup_crtcs() 2417 if (!crtcs || !modes || !enabled || !offsets) { in drm_setup_crtcs() 2432 memset(crtcs, 0, fb_helper->connector_count*sizeof(crtcs[0])); in drm_setup_crtcs() [all …]
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H A D | drm_atomic_helper.c | 1236 old_state->crtcs[i].last_vblank_count = drm_crtc_vblank_count(crtc); in drm_atomic_helper_wait_for_vblanks() 1244 old_state->crtcs[i].last_vblank_count != in drm_atomic_helper_wait_for_vblanks() 2434 state->crtcs[i].state = old_crtc_state; in drm_atomic_helper_swap_state() 3014 state->crtcs[i].old_state = crtc->state; in drm_atomic_helper_commit_duplicated_state()
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/dragonfly/sys/dev/drm/i915/ |
H A D | intel_fbdev.c | 349 struct drm_fb_helper_crtc **crtcs, in intel_fb_initial_config() argument 433 if (crtcs[j] == new_crtc) { in intel_fb_initial_config() 481 crtcs[i] = new_crtc; in intel_fb_initial_config()
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/dragonfly/sys/dev/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm_irq.c | 548 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id]; in dm_irq_state()
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