| /dragonfly/sys/dev/drm/radeon/ |
| H A D | trinity_dpm.c | 999 if ((old_rps->evclk != new_rps->evclk) || in trinity_set_vce_clock()
1002 if (new_rps->evclk || new_rps->ecclk) in trinity_set_vce_clock()
1006 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in trinity_set_vce_clock()
1510 u32 evclk, u32 ecclk, u16 *voltage) in trinity_get_vce_clock_voltage() argument
1517 if (((evclk == 0) && (ecclk == 0)) || in trinity_get_vce_clock_voltage()
1524 if ((evclk <= table->entries[i].evclk) && in trinity_get_vce_clock_voltage()
1560 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in trinity_apply_state_adjust_rules()
1563 new_rps->evclk = 0; in trinity_apply_state_adjust_rules()
1581 trinity_get_vce_clock_voltage(rdev, new_rps->evclk, new_rps->ecclk, &min_vce_voltage); in trinity_apply_state_adjust_rules()
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| H A D | kv_dpm.c | 903 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()
907 (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk); in kv_populate_vce_table()
910 table->entries[i].evclk, false, ÷rs); in kv_populate_vce_table()
1456 static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk) in kv_get_vce_boot_level() argument
1463 if (table->entries[i].evclk >= evclk) in kv_get_vce_boot_level()
1479 if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) { in kv_update_vce_dpm()
1486 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk); in kv_update_vce_dpm()
1503 } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) { in kv_update_vce_dpm()
2151 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in kv_apply_state_adjust_rules()
2154 new_rps->evclk = 0; in kv_apply_state_adjust_rules()
[all …]
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| H A D | si_dpm.c | 2935 u32 evclk, u32 ecclk, u16 *voltage) in si_get_vce_clock_voltage() argument
2942 if (((evclk == 0) && (ecclk == 0)) || in si_get_vce_clock_voltage()
2949 if ((evclk <= table->entries[i].evclk) && in si_get_vce_clock_voltage()
3006 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
3008 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3011 rps->evclk = 0; in si_apply_state_adjust_rules()
5931 if ((old_rps->evclk != new_rps->evclk) || in si_set_vce_clock()
5934 if (new_rps->evclk || new_rps->ecclk) in si_set_vce_clock()
5938 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in si_set_vce_clock()
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| H A D | radeon_asic.h | 720 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
783 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
830 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
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| H A D | radeon.h | 1355 u32 evclk; member
1450 u32 evclk; member
1539 u32 evclk; member
1972 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
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| H A D | ci_dpm.c | 840 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in ci_apply_state_adjust_rules()
843 rps->evclk = 0; in ci_apply_state_adjust_rules()
2737 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; in ci_populate_smc_vce_level()
4138 if (table->entries[i].evclk >= min_evclk) in ci_get_vce_boot_level()
4153 if (radeon_current_state->evclk != radeon_new_state->evclk) { in ci_update_vce_dpm()
4154 if (radeon_new_state->evclk) { in ci_update_vce_dpm()
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| H A D | r600_dpm.c | 1108 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = in r600_parse_extended_power_table()
1123 rdev->pm.dpm.vce_states[i].evclk = in r600_parse_extended_power_table()
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| H A D | si.c | 7485 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) in si_set_vce_clocks() argument
7499 if (!evclk || !ecclk) { in si_set_vce_clocks()
7506 r = radeon_uvd_calc_upll_dividers(rdev, evclk, ecclk, 125000, 250000, in si_set_vce_clocks()
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| /dragonfly/sys/dev/drm/amd/powerplay/inc/ |
| H A D | power_state.h | 173 unsigned long evclk; member
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| H A D | hwmgr.h | 100 uint32_t evclk; member
154 uint32_t evclk; member
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | amdgpu_dpm.h | 63 u32 evclk; member
160 u32 evclk; member
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| H A D | amdgpu_dpm.c | 570 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = in amdgpu_parse_extended_power_table()
586 adev->pm.dpm.vce_states[i].evclk = in amdgpu_parse_extended_power_table()
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| H A D | si_dpm.c | 3034 u32 evclk, u32 ecclk, u16 *voltage) in si_get_vce_clock_voltage() argument
3041 if (((evclk == 0) && (ecclk == 0)) || in si_get_vce_clock_voltage()
3048 if ((evclk <= table->entries[i].evclk) && in si_get_vce_clock_voltage()
3465 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
3467 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3470 rps->evclk = 0; in si_apply_state_adjust_rules()
7975 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); in si_check_state_equal()
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| H A D | soc15.c | 437 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc15_set_vce_clocks() argument
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| H A D | cik.c | 1340 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in cik_set_vce_clocks() argument
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| H A D | vi.c | 789 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in vi_set_vce_clocks() argument
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| H A D | amdgpu_kms.c | 664 vce_clk_table.entries[i].eclk = vce_state->evclk; in amdgpu_info_ioctl()
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| H A D | amdgpu.h | 1156 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
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| /dragonfly/sys/dev/drm/amd/powerplay/hwmgr/ |
| H A D | smu10_hwmgr.h | 131 uint32_t evclk; member
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| H A D | smu8_hwmgr.h | 147 uint32_t evclk; member
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| H A D | smu7_hwmgr.h | 73 uint32_t evclk; member
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| H A D | vega10_hwmgr.h | 101 uint32_t evclk; member
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| H A D | processpptables.c | 1160 vce_table->entries[i].evclk = ((unsigned long)entry->ucEVClkHigh << 16) in get_vce_clock_voltage_limit_table()
1608 vce_state->evclk = ((uint32_t)vce_clock_info->ucEVClkHigh << 16) | vce_clock_info->usEVClkLow; in get_vce_state_table_entry()
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| H A D | process_pptables_v1_0.c | 1261 vce_state->evclk = mm_dep_record->ulEClk; in ppt_get_vce_state_table_entry_v1_0()
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| /dragonfly/sys/dev/drm/amd/include/ |
| H A D | kgd_pp_interface.h | 31 u32 evclk; member
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