/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfoVVLPatterns.td | 654 (mask_type V0), 1163 (fvti.Mask V0), 1197 (ivti.Mask V0), 1247 (fvti.Mask V0), 1283 (ivti.Mask V0), 1322 (fwti.Mask V0), 1357 (iwti.Mask V0), 1409 (vti.Mask V0), 1820 (vti.Mask V0), 1832 (vti.Mask V0), [all …]
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H A D | RISCVInstrInfoZvk.td | 542 (vti.Mask V0), 567 (vti.Mask V0), 582 (vti.Mask V0), 624 (vti.Mask V0), VLOpFrag), 633 (vti.Mask V0), VLOpFrag), 642 (vti.Mask V0), VLOpFrag), 651 (vti.Mask V0), VLOpFrag), 660 (vti.Mask V0), VLOpFrag), 669 (vti.Mask V0), VLOpFrag), 814 (vti.Mask V0), [all …]
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H A D | RISCVFoldMasks.cpp | 65 assert(MaskDef->isCopy() && MaskDef->getOperand(0).getReg() == RISCV::V0); in isAllOnesMask() 117 assert(MI.getOperand(4).isReg() && MI.getOperand(4).getReg() == RISCV::V0); in convertVMergeToVMv() 208 if (MI.definesRegister(RISCV::V0, TRI)) in runOnMachineFunction()
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H A D | RISCVInstrInfoVPseudos.td | 1171 // Mask can be V0~V31 4029 (mask_type V0), 4050 (mask_type V0), 4059 (mask_type V0), 4081 (mti.Mask V0), 4222 (mask_type V0), 4244 (mask_type V0), 4266 (mask_type V0), 4273 (mask_type V0), 4292 (mask_type V0), [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsMachineFunction.cpp | 84 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() local 95 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) in initGlobalBaseReg() 97 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) in initGlobalBaseReg() 109 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg() 111 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) in initGlobalBaseReg() 124 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg() 126 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); in initGlobalBaseReg() 151 MF.getRegInfo().addLiveIn(Mips::V0); in initGlobalBaseReg() 152 MBB.addLiveIn(Mips::V0); in initGlobalBaseReg() 154 .addReg(Mips::V0).addReg(Mips::T9); in initGlobalBaseReg()
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H A D | Mips16ISelDAGToDAG.cpp | 75 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF); in initGlobalBaseReg() local 78 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() 83 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0) in initGlobalBaseReg() 88 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16); in initGlobalBaseReg()
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H A D | MipsRegisterInfo.td | 90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 125 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 288 V0, V1, A0, A1, A2, A3, 308 V0, V1, A0, A1, A2, A3, 324 V0, V1, A0, A1, A2, A3)>; 332 V0, V1, A0, A1, A2, A3)>; 340 V0, V1, 370 V0, V1, A0, A1, A2, A3, 376 V0, V1, A0, A1, A2, A3,
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H A D | MipsCallingConv.td | 99 // i32 are returned in registers V0, V1, A0, A1, unless the original return 102 CCAssignToReg<[V0, V1, A0, A1]>>>, 269 // except for AT, V0 and T9, are available to be used as argument registers. 315 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>> 385 CalleeSavedRegs<(add V0, V1, FP,
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H A D | MipsBranchExpansion.cpp | 737 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0) in emitGPDisp() 739 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0) in emitGPDisp() 740 .addReg(Mips::V0) in emitGPDisp() 742 MBB.removeLiveIn(Mips::V0); in emitGPDisp()
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H A D | MipsAsmPrinter.cpp | 920 EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0); in EmitSwapFPIntRetval() 923 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval() 926 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval() 929 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonVectorPrint.cpp | 74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg() 81 if (R >= Hexagon::V0 && R <= Hexagon::V31) { in getStringReg() 86 return S[R-Hexagon::V0]; in getStringReg() 183 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { in runOnMachineFunction() 184 LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n'); in runOnMachineFunction() 188 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, in runOnMachineFunction() 190 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, in runOnMachineFunction()
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H A D | HexagonCallingConv.td | 116 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>, 130 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>, 148 CCAssignToReg<[V0]>>>, 156 CCAssignToReg<[V0]>>>,
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H A D | HexagonISelDAGToDAG.cpp | 2216 SDValue V0 = L0.Value; in balanceSubTree() local 2222 if ((RootWeights.count(V0.getNode()) && RootWeights[V0.getNode()] == -2) || in balanceSubTree() 2228 ConstantSDNode *V0C = dyn_cast<ConstantSDNode>(V0); in balanceSubTree() 2234 std::swap(V0, V1); in balanceSubTree() 2239 assert(NodeHeights.count(V0) && NodeHeights.count(V1) && in balanceSubTree() 2241 int Height = std::max(NodeHeights[V0], NodeHeights[V1]) + 1; in balanceSubTree() 2246 ISD::SHL, SDLoc(V0), VT, V0, in balanceSubTree() 2249 TLI.getScalarShiftAmountTy(DL, V0.getValueType()))); in balanceSubTree() 2251 NewNode = CurDAG->getNode(NOpcode, SDLoc(N), VT, V0, V1); in balanceSubTree() 2274 SDValue V0 = NewRoot.getOperand(0); in balanceSubTree() local [all …]
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/freebsd/lib/msun/src/ |
H A D | e_j1.c | 130 static const double V0[5] = { variable 188 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4])))); in y1()
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H A D | e_j1f.c | 93 static const float V0[5] = { variable 144 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4])))); in y1f()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
H A D | CSKYISelDAGToDAG.cpp | 49 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1); 191 SDValue V0 = N->getOperand(i + 1); in selectInlineAsm() local 193 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in selectInlineAsm() 376 SDNode *CSKYDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode() argument 377 SDLoc dl(V0.getNode()); in createGPRPairNode() 382 const SDValue Ops[] = {RegClass, V0, SubReg0, V1, SubReg1}; in createGPRPairNode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VECallingConv.td | 107 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>, 110 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>, 128 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>, 131 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
H A D | VectorCombine.cpp | 530 Value *VecCmp = Builder.CreateCmp(Pred, V0, V1); in foldExtExtCmp() 573 Value *V0, *V1; in foldExtractExtract() local 575 if (!match(I0, m_ExtractElt(m_Value(V0), m_ConstantInt(C0))) || in foldExtractExtract() 577 V0->getType() != V1->getType()) in foldExtractExtract() 889 Value *V0 = nullptr, *V1 = nullptr; in scalarizeBinopOrCmp() local 891 if (!match(Ins0, m_InsertElt(m_Constant(VecC0), m_Value(V0), in scalarizeBinopOrCmp() 900 bool IsConst0 = !V0; in scalarizeBinopOrCmp() 909 auto *I0 = dyn_cast_or_null<Instruction>(V0); in scalarizeBinopOrCmp() 916 Type *ScalarTy = IsConst0 ? V1->getType() : V0->getType(); in scalarizeBinopOrCmp() 919 (IsConst0 || IsConst1 || V0->getType() == V1->getType()) && in scalarizeBinopOrCmp() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
H A D | RISCVDisassembler.cpp | 202 MCRegister Reg = RISCV::V0 + RegNo; in DecodeVRRegisterClass() 217 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM2RegisterClass() 234 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM4RegisterClass() 251 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM8RegisterClass() 264 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister; in decodeVMaskReg()
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/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/ |
H A D | Darwin.h | 484 bool isIPhoneOSVersionLT(unsigned V0, unsigned V1 = 0, 487 return TargetVersion < VersionTuple(V0, V1, V2); 494 bool isMacosxVersionLT(unsigned V0, unsigned V1 = 0, unsigned V2 = 0) const { 505 : TargetVersion) < VersionTuple(V0, V1, V2);
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 1848 SDLoc dl(V0.getNode()); in createGPRPairNode() 1859 SDLoc dl(V0.getNode()); in createSRegPairNode() 1870 SDLoc dl(V0.getNode()); in createDRegPairNode() 1881 SDLoc dl(V0.getNode()); in createQRegPairNode() 1893 SDLoc dl(V0.getNode()); in createQuadSRegsNode() 1908 SDLoc dl(V0.getNode()); in createQuadDRegsNode() 1923 SDLoc dl(V0.getNode()); in createQuadQRegsNode() 2312 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVST() local 2368 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVST() local 2487 SDValue V0 = N->getOperand(Vec0Idx + 0); in SelectVLDSTLane() local [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineAddSub.cpp | 391 Value *V0 = I->getOperand(0); in drillValueDownOneStep() local 393 if (ConstantFP *C = dyn_cast<ConstantFP>(V0)) { in drillValueDownOneStep() 399 Addend0.set(C, V0); in drillValueDownOneStep() 469 Value *V0 = I->getOperand(0); in simplify() local 471 InstQuota = ((!isa<Constant>(V0) && V0->hasOneUse()) && in simplify() 2291 Value *V0, *V1; in visitSub() local 2293 V0->getType() == V1->getType()) { in visitSub() 2296 Value *Sub = Builder.CreateSub(V0, V1); in visitSub() 2942 Value *A0, *A1, *V0, *V1; in visitFSub() local 2944 V0->getType() == V1->getType()) { in visitFSub() [all …]
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H A D | InstCombineVectorOps.cpp | 84 Value *V0, *V1; in cheapToScalarize() local 85 if (match(V, m_OneUse(m_BinOp(m_Value(V0), m_Value(V1))))) in cheapToScalarize() 86 if (cheapToScalarize(V0, EI) || cheapToScalarize(V1, EI)) in cheapToScalarize() 90 if (match(V, m_OneUse(m_Cmp(UnusedPred, m_Value(V0), m_Value(V1))))) in cheapToScalarize() 91 if (cheapToScalarize(V0, EI) || cheapToScalarize(V1, EI)) in cheapToScalarize() 2047 Value *V0 = nullptr, Value *V1 = nullptr) : in BinopElts() 2048 Opcode(Opc), Op0(V0), Op1(V1) {} in BinopElts() 2585 Value *V0 = Shuf.getOperand(0), *V1 = Shuf.getOperand(1); in foldShuffleWithInsert() local 2590 int InpNumElts = cast<FixedVectorType>(V0->getType())->getNumElements(); in foldShuffleWithInsert() 2621 if (!match(V0, m_InsertElt(m_Value(), m_Value(Scalar), in foldShuffleWithInsert() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 226 SDValue V0 = N->getOperand(i+1); in tryInlineAsm() local 228 Register Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm()
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/freebsd/sys/contrib/device-tree/src/arm/aspeed/ |
H A D | aspeed-bmc-qcom-dc-scm-v1.dts | 116 /*V0-V7*/ "","","","SCMFPGA_SPARE_GPIO1_3V3",
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