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Searched refs:wb_dat_o (Results 1 – 25 of 83) sorted by relevance

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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/control_lib/
H A Dwb_readback_mux.v28 output reg [31:0] wb_dat_o, port
57 0 : wb_dat_o <= word00;
58 1 : wb_dat_o <= word01;
59 2 : wb_dat_o <= word02;
60 3 : wb_dat_o <= word03;
61 4 : wb_dat_o <= word04;
62 5 : wb_dat_o <= word05;
63 6 : wb_dat_o <= word06;
64 7 : wb_dat_o <= word07;
65 8 : wb_dat_o <= word08;
[all …]
H A Dsd_spi_wb.v42 output reg [7:0] wb_dat_o, port
68 ADDR_STATUS : wb_dat_o <= {7'd0,ready};
69 ADDR_CLKDIV : wb_dat_o <= clkdiv;
70 ADDR_READ : wb_dat_o <= rcv_dat;
71 default : wb_dat_o <= 0;
H A Dwb_semaphore.v39 output [DBUS_WIDTH-1:0] wb_dat_o); port
52 assign wb_dat_o[DBUS_WIDTH-1:1] = {(DBUS_WIDTH-1){1'b0}};
53 assign wb_dat_o[0] = locked[adr_i];
H A Dwb_output_pins32.v28 (wb_rst_i, wb_clk_i, wb_dat_i, wb_dat_o,
35 output wire [31:0] wb_dat_o; port
61 assign wb_dat_o = internal_reg;
H A Dwb_bus_writer.v33 output [31:0] wb_dat_o, port
66 assign wb_dat_o = rom_data[31:0];
H A Dwb_readback_mux_16LE.v31 output [15:0] wb_dat_o, port
61 assign wb_dat_o = data[15:0];
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/io_port2/
H A Dpcie_wb_reg_core_tb.v23 wire [31:0] wb_dat_o; net
119 `CHECK_VALUE(wb_dat_o, 32'h6, "Verify WB status after PCIe read request");
144 `CHECK_VALUE(wb_dat_o, 32'h2, "Verify WB status value after PCIe write request");
163 `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after initiating write");
187 `CHECK_VALUE(wb_dat_o, 32'h1, "Verify WB status value before PCIe responds");
190 `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after PCIe responds");
192 `CHECK_VALUE(wb_dat_o, 32'hace06666, "Verify WB read value after PCIe responds");
196 `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status before request flood");
201 `CHECK_VALUE(wb_dat_o, 32'h11, "Verify WB status after request flood");
206 `CHECK_VALUE(wb_dat_o, 32'h1, "Verify WB status after consuming requests");
[all …]
H A Dpcie_wb_reg_core.v21 output [WB_DATAW-1:0] wb_dat_o, port
49 .wb_dat_i(wb_dat_i), .wb_ack_o(wb_ack_o), .wb_dat_o(wb_dat_o),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/io_port2/pcie_wb_reg_core/
H A Dpcie_wb_reg_core_tb.v23 wire [31:0] wb_dat_o; net
119 `CHECK_VALUE(wb_dat_o, 32'h6, "Verify WB status after PCIe read request");
144 `CHECK_VALUE(wb_dat_o, 32'h2, "Verify WB status value after PCIe write request");
163 `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after initiating write");
187 `CHECK_VALUE(wb_dat_o, 32'h1, "Verify WB status value before PCIe responds");
190 `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status value after PCIe responds");
192 `CHECK_VALUE(wb_dat_o, 32'hace06666, "Verify WB read value after PCIe responds");
196 `CHECK_VALUE(wb_dat_o, 32'h0, "Verify WB status before request flood");
201 `CHECK_VALUE(wb_dat_o, 32'h11, "Verify WB status after request flood");
206 `CHECK_VALUE(wb_dat_o, 32'h1, "Verify WB status after consuming requests");
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wishbone/
H A Di2c_master_top.v80 wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
97 output [7:0] wb_dat_o; // databus output port
104 reg [7:0] wb_dat_o; register
166 3'b000: wb_dat_o <= #1 prer[ 7:0];
167 3'b001: wb_dat_o <= #1 prer[15:8];
168 3'b010: wb_dat_o <= #1 ctr;
169 3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
170 3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
171 3'b101: wb_dat_o <= #1 txr;
172 3'b110: wb_dat_o <= #1 cr;
[all …]
H A Dsettings_readback.v25 output [DWIDTH-1:0] wb_dat_o, port
37 assign wb_dat_o = rb_data;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/i2c/rtl/verilog/
H A Di2c_master_top.v80 wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
97 output [7:0] wb_dat_o; // databus output port
104 reg [7:0] wb_dat_o; register
166 3'b000: wb_dat_o <= #1 prer[ 7:0];
167 3'b001: wb_dat_o <= #1 prer[15:8];
168 3'b010: wb_dat_o <= #1 ctr;
169 3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
170 3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
171 3'b101: wb_dat_o <= #1 txr;
172 3'b110: wb_dat_o <= #1 cr;
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge/rtl/verilog/
H A Dwishbone_if.v42 wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable,
63 output [31:0] wb_dat_o; port
201 reg [31:0] wb_dat_o; register
275 wb_dat_o <= 32'b0;
329 wb_dat_o <= {31'b0, cpureg_config0};
333 wb_dat_o <= {23'b0, cpureg_int_pending};
339 wb_dat_o <= {23'b0, int_sources};
343 wb_dat_o <= {23'b0, cpureg_int_mask};
347 wb_dat_o <= {16'b0, mdio_read_data};
351 wb_dat_o <= {31'b0, mdio_running};
[all …]
H A Dxge_mac_wb.v44 wb_int_o, wb_dat_o, wb_ack_o,
91 output [31:0] wb_dat_o; // From wishbone_if0 of wishbone_if.v port
199 .wb_dat_o (wb_dat_o[31:0]),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wb_spi/rtl/verilog/
H A Dspi_top.v52 wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i,
64 output [32-1:0] wb_dat_o; // databus output port
79 reg [32-1:0] wb_dat_o; register
147 wb_dat_o <= 32'b0;
149 wb_dat_o <= wb_dat;
H A Dspi_top16.v54 output reg [15:0] wb_dat_o, port
104 wb_dat_o <= 32'b0;
106 wb_dat_o <= wb_adr_i[1] ? wb_dat[31:16] : wb_dat[15:0];
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/spi/rtl/verilog/
H A Dspi_top.v50 wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i,
62 output [32-1:0] wb_dat_o; // databus output port
77 reg [32-1:0] wb_dat_o; register
145 wb_dat_o <= 32'b0;
147 wb_dat_o <= wb_dat;
H A Dspi_top16.v52 output reg [15:0] wb_dat_o, port
102 wb_dat_o <= 32'b0;
104 wb_dat_o <= wb_adr_i[1] ? wb_dat[31:16] : wb_dat[15:0];
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/i2c/rtl/vhdl/
H A Di2c_master_top.vhd86 wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output port
188 -- assign wb_dat_o
193 when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
194 when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
195 when "010" => wb_dat_o <= ctr;
196 when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
197 when "100" => wb_dat_o <= sr; -- write is command register CR
202 when "101" => wb_dat_o <= txr;
203 when "110" => wb_dat_o <= cr;
204 when "111" => wb_dat_o <= (others => '0');
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/fifo/
H A Dbuffer_pool_tb.v27 wire [31:0] wb_dat_o; net
54 .wb_dat_o(wb_dat_o),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dx300_sfpp_io_core.v56 output [31:0] wb_dat_o, port
169 .wb_dat_o(wb_dat_o),
273 .wb_dat_i(wb_dat_o),
277 .wb_dat_o(wb_dat_i),
424 .wb_adr_i(wb_adr_i), .wb_stb_i(wb_stb_i), .wb_we_i(wb_we_i), .wb_dat_o(wb_dat_o),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/simple_gemac/simple_gemac_wrapper/
H A Dsimple_gemac_wrapper_tb.v46 wire [31:0] wb_dat_o; net
70 .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/simple_gemac/
H A Dsimple_gemac_wrapper_tb.v46 wire [31:0] wb_dat_o; net
70 .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/simple_gemac/
H A Dsimple_gemac_wrapper_tb.v55 wire [31:0] wb_dat_o; net
79 .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
H A Dsimple_gemac_wb.v40 input [7:0] wb_adr, input [31:0] wb_dat_i, output reg [31:0] wb_dat_o, port
172 8 : wb_dat_o <= MIICOMMAND;
173 9 : wb_dat_o <= MIISTATUS;
174 10: wb_dat_o <= MIIRX_DATA;

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