/dports/lang/smalltalk/smalltalk-3.2.5/opcode/ |
H A D | ppc-opc.c | 222 #define FRT (FRS) macro 2444 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } }, 2472 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } }, 2609 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } }, 2611 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, 2613 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } }, 2615 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, 2625 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } }, 2627 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } }, 2764 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, [all …]
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/dports/games/libretro-beetle_saturn/beetle-saturn-libretro-ee5b214/mednafen/ss/ |
H A D | sh7095.inc | 263 FRT.OCR[0] = FRT.OCR[1] = 0; 573 FRT.OCR[0] = FRT.OCR[1] = 0x00; 588 if(FRT.FRC == FRT.OCR[0]) // OCRA 601 if(FRT.FRC == FRT.OCR[1]) // OCRB 647 if(FRT.OCR[0] > FRT.FRC) 650 if(FRT.OCR[1] > FRT.FRC) 762 FRT.FICR = FRT.FRC; 1247 FRT.FTCSR = (FRT.FTCSR & (FRT.FTCSRM | V) & 0x8E) | (V & 0x01); 1275 FRT.OCR[(FRT.TOCR >> 4) & 1] = (FRT.RW_Temp << 8) | V; 1738 FRT.RW_Temp = FRT.FRC; [all …]
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/dports/emulators/mednafen/mednafen/src/ss/ |
H A D | sh7095.inc | 401 FRT.OCR[0] = FRT.OCR[1] = 0; 874 FRT.OCR[0] = FRT.OCR[1] = 0x00; 889 if(FRT.FRC == FRT.OCR[0]) // OCRA 902 if(FRT.FRC == FRT.OCR[1]) // OCRB 948 if(FRT.OCR[0] > FRT.FRC) 951 if(FRT.OCR[1] > FRT.FRC) 1065 FRT.FICR = FRT.FRC; 1530 FRT.FTCSR = (FRT.FTCSR & (FRT.FTCSRM | V) & 0x8E) | (V & 0x01); 1558 FRT.OCR[(FRT.TOCR >> 4) & 1] = (FRT.RW_Temp << 8) | V; 2004 FRT.RW_Temp = FRT.FRC; [all …]
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/dports/devel/gdb761/gdb-7.6.1/opcodes/ |
H A D | ppc-opc.c | 368 #define FRT FRS macro 5736 {"lfs", OP(48), OP_MASK, COM, PPCEFS, {FRT, D, RA0}}, 5738 {"lfsu", OP(49), OP_MASK, COM, PPCEFS, {FRT, D, RAS}}, 5740 {"lfd", OP(50), OP_MASK, COM, PPCEFS, {FRT, D, RA0}}, 5742 {"lfdu", OP(51), OP_MASK, COM, PPCEFS, {FRT, D, RAS}}, 6038 {"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, 6118 {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, 6132 {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, 6133 {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS, {FRT, FRB}}, 6197 {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS, {FRT}}, [all …]
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/dports/devel/vasm/vasm/cpus/ppc/ |
H A D | opcodes.h | 1883 "lfqx", { FRT, RA, RB } ,{POWER2, X(31,791)}, 1885 "lfqux", { FRT, RA, RB } ,{POWER2, X(31,823)}, 2142 "lfsx", { FRT, RA, RB } ,{COM, X(31,535)}, 2160 "lfsux", { FRT, RAS, RB } ,{COM, X(31,567)}, 2175 "lfdx", { FRT, RA, RB } ,{COM, X(31,599)}, 2345 "lfs", { FRT, D, RA } ,{COM, OP(48)}, 2347 "lfsu", { FRT, D, RAS } ,{COM, OP(49)}, 2349 "lfd", { FRT, D, RA } ,{COM, OP(50)}, 2351 "lfdu", { FRT, D, RAS } ,{COM, OP(51)}, 2361 "lfq", { FRT, D, RA } ,{POWER2, OP(56)}, [all …]
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/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/ |
H A D | ppc-opc.c | 406 #define FRT FRS macro 3193 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3230 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3232 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3249 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3250 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3338 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 5019 {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5059 {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5110 {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, [all …]
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/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/ |
H A D | ppc-opc.c | 406 #define FRT FRS macro 3193 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3230 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3232 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3249 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3250 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3338 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 5019 {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5059 {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5110 {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, [all …]
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/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/powerpc/xmon/ |
H A D | ppc-opc.c | 394 #define FRT FRS macro 3141 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3176 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3178 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3195 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3196 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3284 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 4961 {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 4999 {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5048 {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, [all …]
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/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/powerpc/xmon/ |
H A D | ppc-opc.c | 394 #define FRT FRS macro 3141 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3176 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3178 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3195 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3196 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3284 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 4961 {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 4999 {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5048 {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, [all …]
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/dports/multimedia/libv4l/linux-5.13-rc2/arch/powerpc/xmon/ |
H A D | ppc-opc.c | 394 #define FRT FRS macro 3141 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3176 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3178 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3195 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3196 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3284 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 4961 {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 4999 {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5048 {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, [all …]
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/dports/security/clamav-lts/clamav-0.103.5/libclamav/c++/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.td | 1160 "fadd $FRT, $FRA, $FRB", FPGeneral, 1237 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1290 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1299 "fadd $FRT, $FRA, $FRB", FPGeneral, 1303 "fadds $FRT, $FRA, $FRB", FPGeneral, 1307 "fdiv $FRT, $FRA, $FRB", FPDivD, 1311 "fdivs $FRT, $FRA, $FRB", FPDivS, 1315 "fmul $FRT, $FRA, $FRB", FPFused, 1319 "fmuls $FRT, $FRA, $FRB", FPGeneral, 1323 "fsub $FRT, $FRA, $FRB", FPGeneral, [all …]
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/dports/devel/djgpp-binutils/binutils-2.17/opcodes/ |
H A D | ppc-opc.c | 291 #define FRT FRS macro 4215 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 4239 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, 4464 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 4466 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, 4468 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 4470 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, 4482 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } }, 4484 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, 4664 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, [all …]
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/dports/games/iortcw/iortcw-1.51c/MP/code/qcommon/ |
H A D | vm_powerpc_asm.c | 320 #define FRT FRS macro 973 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 987 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 988 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 993 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 994 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 995 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 996 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 999 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, 1000 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, [all …]
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/dports/games/ioquake3/ioquake3-1.36/code/qcommon/ |
H A D | vm_powerpc_asm.c | 321 #define FRT FRS macro 976 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 990 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 991 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 996 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 997 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 998 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 999 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 1002 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, 1003 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, [all …]
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/dports/games/ioquake3-server/ioquake3-1.36/code/qcommon/ |
H A D | vm_powerpc_asm.c | 321 #define FRT FRS macro 976 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 990 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 991 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 996 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 997 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 998 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 999 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 1002 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, 1003 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, [all …]
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/dports/games/iortcw/iortcw-1.51c/SP/code/qcommon/ |
H A D | vm_powerpc_asm.c | 320 #define FRT FRS macro 973 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 987 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 988 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 993 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 994 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 995 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 996 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 999 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, 1000 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, [all …]
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/dports/games/openarena/openarena-engine-source-0.8.8/code/qcommon/ |
H A D | vm_powerpc_asm.c | 321 #define FRT FRS macro 975 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 989 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 990 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 995 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 996 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 997 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 998 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 1001 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, 1002 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, [all …]
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/dports/games/openarena-server/openarena-engine-source-0.8.8/code/qcommon/ |
H A D | vm_powerpc_asm.c | 321 #define FRT FRS macro 975 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 989 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 990 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 995 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 996 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 997 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 998 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 1001 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, 1002 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, [all …]
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | ppc-opc.c | 286 #define FRT FRS macro 4111 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 4135 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, 4362 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 4364 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, 4366 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 4368 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, 4380 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } }, 4382 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, 4547 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, [all …]
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/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/ |
H A D | ppc-opc.c | 289 #define FRT FRS macro 4167 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 4191 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, 4416 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 4418 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, 4420 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 4422 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, 4434 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } }, 4436 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, 4601 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, [all …]
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | ppc-opc.c | 286 #define FRT FRS macro 4111 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 4135 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, 4362 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 4364 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, 4366 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 4368 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, 4380 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } }, 4382 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, 4547 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, [all …]
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/dports/devel/valgrind-lts/valgrind-dragonfly-dragonfly/memcheck/tests/ppc32/ |
H A D | power_ISA2_05.c | 153 double FRT, FRA, FRB; in test_fcpsgn() local 160 __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA), in test_fcpsgn() 162 printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT); in test_fcpsgn()
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/dports/devel/valgrind/valgrind-dragonfly-dragonfly/memcheck/tests/ppc32/ |
H A D | power_ISA2_05.c | 153 double FRT, FRA, FRB; in test_fcpsgn() local 160 __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA), in test_fcpsgn() 162 printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT); in test_fcpsgn()
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/dports/devel/valgrind/valgrind-dragonfly-dragonfly/memcheck/tests/ppc64/ |
H A D | power_ISA2_05.c | 158 double FRT, FRA, FRB; in test_fcpsgn() local 165 __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA), in test_fcpsgn() 167 printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT); in test_fcpsgn()
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/dports/devel/valgrind-lts/valgrind-dragonfly-dragonfly/memcheck/tests/ppc64/ |
H A D | power_ISA2_05.c | 158 double FRT, FRA, FRB; in test_fcpsgn() local 165 __asm__ volatile ("fcpsgn %0, %1, %2":"=f" (FRT):"f"(FRA), in test_fcpsgn() 167 printf("fcpsgn sign=%f, base=%f => %f\n", FRA, FRB, FRT); in test_fcpsgn()
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