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/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/
H A DLan91xDxeHw.h77 #define TCR_EPH_LOOP BIT13
104 #define RCR_ABORT_ENB BIT13
120 #define RPCR_SPEED BIT13
172 #define PTR_READ BIT13
202 #define RX_BAD_CRC BIT13
212 #define PCW_ODD BIT13
244 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
257 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
270 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/
H A DLan91xDxeHw.h77 #define TCR_EPH_LOOP BIT13
104 #define RCR_ABORT_ENB BIT13
120 #define RPCR_SPEED BIT13
172 #define PTR_READ BIT13
202 #define RX_BAD_CRC BIT13
212 #define PCW_ODD BIT13
244 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
257 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
270 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/EmbeddedPkg/Drivers/Lan91xDxe/
H A DLan91xDxeHw.h77 #define TCR_EPH_LOOP BIT13
104 #define RCR_ABORT_ENB BIT13
120 #define RPCR_SPEED BIT13
172 #define PTR_READ BIT13
202 #define RX_BAD_CRC BIT13
212 #define PCW_ODD BIT13
244 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
257 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
270 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/
H A DLan91xDxeHw.h77 #define TCR_EPH_LOOP BIT13
104 #define RCR_ABORT_ENB BIT13
120 #define RPCR_SPEED BIT13
172 #define PTR_READ BIT13
202 #define RX_BAD_CRC BIT13
212 #define PCW_ODD BIT13
244 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
257 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
270 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
/dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/ARM/VExpressPkg/Drivers/Lan91xDxe/
H A DLan91xDxeHw.h84 #define TCR_EPH_LOOP BIT13
111 #define RCR_ABORT_ENB BIT13
127 #define RPCR_SPEED BIT13
179 #define PTR_READ BIT13
209 #define RX_BAD_CRC BIT13
219 #define PCW_ODD BIT13
251 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
264 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
277 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/EmbeddedPkg/Drivers/Lan9118Dxe/
H A DLan9118DxeHw.h72 #define RXSTATUS_BCF BIT13 // Frame has Broadcast Addr…
98 #define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion inter…
111 #define INSTS_TXE BIT13 // Transmitter Error
145 #define MPTCTRL_PM_MODE_MASK (BIT12 | BIT13) // Set the power mode
153 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
166 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
177 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
208 #define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode b…
309 #define TX_CMD_A_FIRST_SEGMENT BIT13
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
H A DLan9118DxeHw.h137 #define RXSTATUS_BCF BIT13 // Frame has Broadcast Addr…
163 #define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion inter…
176 #define INSTS_TXE BIT13 // Transmitter Error
210 #define MPTCTRL_PM_MODE_MASK (BIT12 | BIT13) // Set the power mode
218 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
231 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
242 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
273 #define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode b…
374 #define TX_CMD_A_FIRST_SEGMENT BIT13
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
H A DLan9118DxeHw.h137 #define RXSTATUS_BCF BIT13 // Frame has Broadcast Addr…
163 #define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion inter…
176 #define INSTS_TXE BIT13 // Transmitter Error
210 #define MPTCTRL_PM_MODE_MASK (BIT12 | BIT13) // Set the power mode
218 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
231 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
242 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
273 #define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode b…
374 #define TX_CMD_A_FIRST_SEGMENT BIT13
/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/EmbeddedPkg/Drivers/Lan9118Dxe/
H A DLan9118DxeHw.h137 #define RXSTATUS_BCF BIT13 // Frame has Broadcast Addr…
163 #define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion inter…
176 #define INSTS_TXE BIT13 // Transmitter Error
210 #define MPTCTRL_PM_MODE_MASK (BIT12 | BIT13) // Set the power mode
218 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
231 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
242 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
273 #define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode b…
374 #define TX_CMD_A_FIRST_SEGMENT BIT13
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
H A DLan9118DxeHw.h137 #define RXSTATUS_BCF BIT13 // Frame has Broadcast Addr…
163 #define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion inter…
176 #define INSTS_TXE BIT13 // Transmitter Error
210 #define MPTCTRL_PM_MODE_MASK (BIT12 | BIT13) // Set the power mode
218 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
231 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
242 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
273 #define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode b…
374 #define TX_CMD_A_FIRST_SEGMENT BIT13
/dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/ARM/VExpressPkg/Drivers/Lan9118Dxe/
H A DLan9118DxeHw.h144 #define RXSTATUS_BCF BIT13 // Frame has Broadcast Addr…
170 #define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion inter…
183 #define INSTS_TXE BIT13 // Transmitter Error
217 #define MPTCTRL_PM_MODE_MASK (BIT12 | BIT13) // Set the power mode
225 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
238 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
249 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
280 #define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode b…
381 #define TX_CMD_A_FIRST_SEGMENT BIT13
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/
H A DPchRegsHsio.h45 #define B_HSIO_PCR_LANE_GROUP_NO (BIT13 | BIT12 | BIT11 | BIT10 | BIT9)
93 #define B_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 |…
111 #define B_HSIO_PCR_RX_DWORD34_MM_PH_OFC_SCALE_2_0 (BIT14 | BIT13 | BIT12)
135 #define B_HSIO_PCR_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
141 #define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
150 #define B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
H A DPchRegsFia.h62 #define B_PCH_FIA_PCR_L3O (BIT15 | BIT14 | BIT13 | BIT12)
70 #define B_PCH_FIA_PCR_L11O (BIT15 | BIT14 | BIT13 | BIT12)
78 #define B_PCH_FIA_PCR_L19O (BIT15 | BIT14 | BIT13 | BIT12)
86 #define B_PCH_FIA_PCR_L27O (BIT15 | BIT14 | BIT13 | BIT12)
H A DPchRegsPmc.h85 #define B_ACPI_IO_PM1_CNT_SLP_EN BIT13
107 #define B_ACPI_IO_SMI_EN_TCO BIT13
147 #define B_ACPI_IO_SMI_STS_TCO BIT13
209 #define B_ACPI_IO_OC_WDT_CTL_ICCSURV BIT13
227 #define B_ACPI_IO_GPE0_STS_127_96_PME_B0 BIT13
255 #define B_ACPI_IO_GPE0_EN_127_96_PME_B0 BIT13
378 #define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_BCLKREQ_ON BIT13
397 #define B_PMC_PWRM_GEN_PMCON_B_WOL_EN_OVRD BIT13
438 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_GBE BIT13 ///< GbE ModPHY SPD RT Request
623 #define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_C3_FDIS_PMC BIT13 ///< PCIe Controller C Port 3 Fu…
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/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsPcu.h90 #define B_PCH_LPC_DEV_STS_RMA BIT13 // Received Master Abort
197 #define B_PCH_LPC_FWH_BIOS_DEC_EE8 BIT13 // E8-EF Enable
500 #define B_PCH_ACPI_PM1_CNT_SLP_EN BIT13 // Sleep enable
558 #define B_PCH_SMI_EN_TCO BIT13 // TCO Enable
593 #define B_PCH_SMI_STS_TCO BIT13 // TCO Status
764 #define B_PCH_PMC_FUNC_DIS_LPE BIT13 // LPE Disable
801 #define B_PCH_PMC_GPI_ROUT_6 (BIT13 | BIT12)
857 #define B_PCH_PMC_PSS_PG_STS_OTG_VCCS BIT13 // OTG VCCS
887 #define B_PCH_PMC_D3_STS_0_LPE BIT13 // LPE
924 #define B_PCH_PMC_D3_STDBY_STS_0_LPE BIT13 // LPE
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H A DPchRegsSpi.h48 #define B_PCH_SPI_HSFS_FDOPSS BIT13 // Flash Descriptor Override Pin-Strap Status
77 #define B_PCH_SPI_OPTYPE6_MASK (BIT13 | BIT12) // Opcode Type 6 Mask
97 #define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) // Flash Descriptor Section Se…
H A DPchRegsSata.h82 #define B_PCH_SATA_PCISTS_RMA BIT13 // Received Master-Abort Status
170 #define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) /…
172 #define B_PCH_SATA_PORT5_DISABLED BIT13
188 #define B_PCH_SATA_PCS_PORT5_DET BIT13 // Port 5 Present
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsPcu.h84 #define B_PCH_LPC_DEV_STS_RMA BIT13 // Received Master Abort
191 #define B_PCH_LPC_FWH_BIOS_DEC_EE8 BIT13 // E8-EF Enable
494 #define B_PCH_ACPI_PM1_CNT_SLP_EN BIT13 // Sleep enable
552 #define B_PCH_SMI_EN_TCO BIT13 // TCO Enable
587 #define B_PCH_SMI_STS_TCO BIT13 // TCO Status
758 #define B_PCH_PMC_FUNC_DIS_LPE BIT13 // LPE Disable
795 #define B_PCH_PMC_GPI_ROUT_6 (BIT13 | BIT12)
851 #define B_PCH_PMC_PSS_PG_STS_OTG_VCCS BIT13 // OTG VCCS
881 #define B_PCH_PMC_D3_STS_0_LPE BIT13 // LPE
918 #define B_PCH_PMC_D3_STDBY_STS_0_LPE BIT13 // LPE
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H A DPchRegsSpi.h42 #define B_PCH_SPI_HSFS_FDOPSS BIT13 // Flash Descriptor Override Pin-Strap Status
71 #define B_PCH_SPI_OPTYPE6_MASK (BIT13 | BIT12) // Opcode Type 6 Mask
91 #define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) // Flash Descriptor Section Se…
H A DPchRegsSata.h76 #define B_PCH_SATA_PCISTS_RMA BIT13 // Received Master-Abort Status
164 #define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) /…
166 #define B_PCH_SATA_PORT5_DISABLED BIT13
182 #define B_PCH_SATA_PCS_PORT5_DET BIT13 // Port 5 Present
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/
H A DPchRegsHsio.h15 #define B_PCH_HSIO_LANE_GROUP_NO (BIT13 | BIT12 | BIT11 | BIT10 | BIT9)
69 #define B_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 |…
87 #define B_PCH_HSIO_RX_DWORD34_MM_PH_OFC_SCALE_2_0 (BIT14 | BIT13 | BIT12)
111 #define B_PCH_HSIO_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
117 #define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
126 #define B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
H A DPchRegsPmc.h63 #define B_PCH_PMC_GEN_PMCON_A_ALLOW_OPI_PLL_SD_INC0 BIT13
83 #define B_PCH_PMC_GEN_PMCON_B_WOL_EN_OVRD BIT13
161 #define B_PCH_ACPI_PM1_CNT_SLP_EN BIT13
183 #define B_PCH_SMI_EN_TCO BIT13
223 #define B_PCH_SMI_STS_TCO BIT13
285 #define B_PCH_OC_WDT_CTL_ICCSURV BIT13
301 #define B_PCH_ACPI_GPE0_STS_127_96_PME_B0 BIT13
328 #define B_PCH_ACPI_GPE0_EN_127_96_PME_B0 BIT13
529 #define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_GBE BIT13 ///< GbE ModPHY SPD RT Request
602 #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C3_FUSE_DIS BIT13 ///< PCIe Controller C Port 3 Fus…
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H A DPchRegsFia.h86 #define B_PCH_PCR_FIA_L3O (BIT15 | BIT14 | BIT13 | BIT12)
94 #define B_PCH_PCR_FIA_L11O (BIT15 | BIT14 | BIT13 | BIT12)
102 #define B_PCH_PCR_FIA_L19O (BIT15 | BIT14 | BIT13 | BIT12)
110 #define B_PCH_PCR_FIA_L27O (BIT15 | BIT14 | BIT13 | BIT12)
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/SimicsIch10Pkg/Include/Register/
H A DPchRegsPmc.h64 #define B_PCH_PMC_GEN_PMCON_A_ALLOW_OPI_PLL_SD_INC0 BIT13
84 #define B_PCH_PMC_GEN_PMCON_B_WOL_EN_OVRD BIT13
162 #define B_PCH_ACPI_PM1_CNT_SLP_EN BIT13
184 #define B_PCH_SMI_EN_TCO BIT13
224 #define B_PCH_SMI_STS_TCO BIT13
286 #define B_PCH_OC_WDT_CTL_ICCSURV BIT13
302 #define B_PCH_ACPI_GPE0_STS_127_96_PME_B0 BIT13
329 #define B_PCH_ACPI_GPE0_EN_127_96_PME_B0 BIT13
530 #define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_GBE BIT13 ///< GbE ModPHY SPD RT Request
603 #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C3_FUSE_DIS BIT13 ///< PCIe Controller C Port 3 Fus…
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/
H A DPmcRegs.h62 #define B_ACPI_IO_PM1_CNT_SLP_EN BIT13
78 #define B_ACPI_IO_SMI_EN_TCO BIT13
101 #define B_ACPI_IO_SMI_STS_TCO BIT13
137 #define B_ACPI_IO_GPE0_STS_127_96_PME_B0 BIT13
150 #define B_ACPI_IO_GPE0_EN_127_96_PME_B0 BIT13

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