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Searched refs:SMU__NUM_SCLK_DPM_STATE (Results 1 – 20 of 20) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dkv_dpm.h26 #define SMU__NUM_SCLK_DPM_STATE 8 macro
131 SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
H A Dsmu7.h41 #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
H A Dsmu7_fusion.h233 SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE];
H A Dci_dpm.h28 #define SMU__NUM_SCLK_DPM_STATE 8 macro
H A Dsmu7_discrete.h235 …SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
H A Dkv_dpm.c2806 if (current_index >= SMU__NUM_SCLK_DPM_STATE) { in kv_dpm_debugfs_print_current_performance_level()
2828 if (current_index >= SMU__NUM_SCLK_DPM_STATE) { in kv_dpm_get_current_sclk()
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Dci_smumgr.h26 #define SMU__NUM_SCLK_DPM_STATE 8 macro
/dragonfly/sys/dev/drm/amd/powerplay/inc/
H A Dsmu71.h31 #define SMU__NUM_SCLK_DPM_STATE 8 macro
61 #define SMU71_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
H A Dsmu7.h41 #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
H A Dsmu72.h31 #define SMU__NUM_SCLK_DPM_STATE 8 macro
109 #define SMU72_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
H A Dsmu73.h93 #define SMU__NUM_SCLK_DPM_STATE 8 macro
108 #define SMU73_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
H A Dsmu75.h40 #define SMU__NUM_SCLK_DPM_STATE 8 macro
55 #define SMU75_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
H A Dsmu74.h32 #define SMU__NUM_SCLK_DPM_STATE 8 macro
134 #define SMU74_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
H A Dsmu7_fusion.h233 SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE];
H A Dsmu7_discrete.h235 …SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
H A Dsmu71_discrete.h179 …SMU71_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS…
H A Dsmu72_discrete.h166 …SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS…
H A Dsmu73_discrete.h156 …SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS…
H A Dsmu74_discrete.h179 …SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS…
H A Dsmu75_discrete.h192 …SMU75_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS…