/dragonfly/sys/dev/drm/radeon/ |
H A D | rs780_dpm.c | 571 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_before_set_eng_clock() 577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock() 588 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_after_set_eng_clock() 594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock() 728 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rs780_parse_pplib_non_clock_info() 731 rps->dclk = 0; in rs780_parse_pplib_non_clock_info() 735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info() 737 rps->dclk = RS780_DEFAULT_DCLK_FREQ; in rs780_parse_pplib_non_clock_info() 944 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state() 993 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
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H A D | trinity_dpm.c | 903 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero() 916 (rps1->dclk == rps2->dclk) && in trinity_uvd_clocks_equal() 948 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks() 959 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks() 1464 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk)) in trinity_get_uvd_clock_index() 1698 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in trinity_parse_pplib_non_clock_info() 1701 rps->dclk = 0; in trinity_parse_pplib_non_clock_info() 1940 pi->sys_info.uvd_clock_table_entries[i].dclk = in trinity_parse_sys_info_table() 2023 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state() 2048 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
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H A D | sumo_dpm.c | 827 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks() 844 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_before_set_eng_clock() 862 (new_rps->dclk == old_rps->dclk)) in sumo_set_uvd_clock_after_set_eng_clock() 1418 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in sumo_parse_pplib_non_clock_info() 1421 rps->dclk = 0; in sumo_parse_pplib_non_clock_info() 1804 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state() 1827 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level() 1835 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
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H A D | rv770_dpm.c | 1444 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_before_set_eng_clock() 1450 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock() 1461 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_after_set_eng_clock() 1467 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock() 2159 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rv7xx_parse_pplib_non_clock_info() 2162 rps->dclk = 0; in rv7xx_parse_pplib_non_clock_info() 2166 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info() 2168 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in rv7xx_parse_pplib_non_clock_info() 2444 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state() 2488 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
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H A D | rv6xx_dpm.c | 1520 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_before_set_eng_clock() 1526 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock() 1537 (new_ps->dclk == old_ps->dclk)) in rv6xx_set_uvd_clock_after_set_eng_clock() 1543 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock() 1805 rps->dclk = RV6XX_DEFAULT_DCLK_FREQ; in rv6xx_parse_pplib_non_clock_info() 1808 rps->dclk = 0; in rv6xx_parse_pplib_non_clock_info() 2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state() 2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
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H A D | radeon_uvd.c | 960 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument 975 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers() 996 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, in radeon_uvd_calc_upll_dividers() 1002 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
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H A D | trinity_dpm.h | 70 u32 dclk; member
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H A D | radeon_asic.h | 413 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 480 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 536 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 537 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 782 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 829 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
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H A D | rv770.c | 44 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in rv770_set_uvd_clocks() argument 51 return evergreen_set_uvd_clocks(rdev, vclk, dclk); in rv770_set_uvd_clocks() 58 if (!vclk || !dclk) { in rv770_set_uvd_clocks() 64 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in rv770_set_uvd_clocks()
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H A D | ni_dpm.c | 3514 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_before_set_eng_clock() 3521 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock() 3532 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_after_set_eng_clock() 3539 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock() 3903 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in ni_parse_pplib_non_clock_info() 3906 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in ni_parse_pplib_non_clock_info() 3909 rps->dclk = 0; in ni_parse_pplib_non_clock_info() 4286 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_print_power_state() 4314 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_debugfs_print_current_performance_level()
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H A D | kv_dpm.c | 833 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table() 839 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk); in kv_populate_uvd_table() 848 table->entries[i].dclk, false, ÷rs); in kv_populate_uvd_table() 2218 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules() 2592 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in kv_parse_pplib_non_clock_info() 2595 rps->dclk = 0; in kv_parse_pplib_non_clock_info() 2851 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in kv_dpm_print_power_state()
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H A D | radeon.h | 1353 u32 dclk; member 1439 u32 dclk; member 1706 unsigned vclk, unsigned dclk, 1971 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
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/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/ |
H A D | hwmgr_ppt.h | 59 uint32_t dclk; /* UVD D-clock */ member
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H A D | smu8_hwmgr.c | 525 (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0; in smu8_upload_pptable_to_smu() 1383 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu8_dpm_get_pp_table_entry() 1686 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; in smu8_read_sensor() local 1732 dclk = uvd_table->entries[uvd_index].dclk; in smu8_read_sensor() 1733 *((uint32_t *)value) = dclk; in smu8_read_sensor()
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H A D | smu10_hwmgr.h | 98 uint32_t dclk; member
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H A D | smu8_hwmgr.h | 115 uint32_t dclk; member
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H A D | smu7_hwmgr.h | 69 uint32_t dclk; member
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H A D | vega10_hwmgr.h | 97 uint32_t dclk; member
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/dragonfly/sys/dev/drm/amd/powerplay/inc/ |
H A D | power_state.h | 177 unsigned long dclk; member
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H A D | hwmgr.h | 106 uint32_t dclk; member 133 uint32_t dclk; member
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/dragonfly/sys/dev/drm/amd/display/dc/ |
H A D | dm_services_types.h | 66 struct dm_pp_clock_range dclk; member
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | amdgpu_dpm.h | 61 u32 dclk; member 149 u32 dclk; member
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H A D | vi.c | 764 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in vi_set_uvd_clocks() argument 773 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS); in vi_set_uvd_clocks() 781 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); in vi_set_uvd_clocks()
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H A D | si_dpm.c | 2370 amdgpu_state->vclk && amdgpu_state->dclk) in si_should_disable_uvd_powertune() 3178 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_before_set_eng_clock() 3185 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock() 3196 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_after_set_eng_clock() 3478 if (rps->vclk || rps->dclk) { in si_apply_state_adjust_rules() 5630 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0)) in si_is_state_ulv_compatible() 5667 if (amdgpu_state->vclk && amdgpu_state->dclk) { in si_convert_power_state_to_smc() 7114 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in si_parse_pplib_non_clock_info() 7117 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in si_parse_pplib_non_clock_info() 7120 rps->dclk = 0; in si_parse_pplib_non_clock_info() [all …]
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H A D | cik.c | 1328 static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in cik_set_uvd_clocks() argument 1336 r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); in cik_set_uvd_clocks()
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