Home
last modified time | relevance | path

Searched refs:lane_count (Results 1 – 25 of 28) sorted by relevance

12

/dragonfly/sys/dev/drm/amd/display/dc/core/
H A Ddc_link_dp.c512 link_settings.lane_count); in dpcd_set_lane_settings()
634 lane_count, in perform_post_lt_adj_req_sequence()
727 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_channel_equalization_sequence() local
945 lt_settings.link_settings.lane_count = link_setting->lane_count; in dc_link_dp_perform_link_training()
1079 if (link->reported_link_cap.lane_count < max_link_cap.lane_count) in get_max_link_cap()
1080 max_link_cap.lane_count = in get_max_link_cap()
1253 switch (lane_count) { in reduce_lane_count()
1283 switch (lane_count) { in increase_lane_count()
1444 uint32_t lane_count = link_setting->lane_count; in bandwidth_in_kbps_from_link_settings() local
1447 kbps *= lane_count; in bandwidth_in_kbps_from_link_settings()
[all …]
H A Ddc_link.c1439 if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) in enable_link_dp_mst()
2167 link_rate_in_mbps * link_settings->lane_count); in get_pbn_per_slot()
H A Ddc.c432 if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) && in dc_link_set_preferred_link_settings()
/dragonfly/sys/dev/drm/i915/
H A Dintel_dp_link_training.c45 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_get_adjust_train()
84 len = intel_dp->lane_count + 1; in intel_dp_set_link_train()
110 intel_dp->train_set, intel_dp->lane_count); in intel_dp_update_link_train()
112 return ret == intel_dp->lane_count; in intel_dp_update_link_train()
119 for (lane = 0; lane < intel_dp->lane_count; lane++) in intel_dp_link_max_vswing_reached()
144 link_config[1] = intel_dp->lane_count; in intel_dp_link_training_clock_recovery()
273 intel_dp->lane_count)) { in intel_dp_link_training_channel_equalization()
281 intel_dp->lane_count)) { in intel_dp_link_training_channel_equalization()
327 intel_dp->link_rate, intel_dp->lane_count); in intel_dp_start_link_train()
339 intel_dp->lane_count)) in intel_dp_start_link_train()
[all …]
H A Dintel_dpio_phy.c571 uint8_t lane_count) in bxt_ddi_phy_calc_lane_lat_optim_mask() argument
573 switch (lane_count) { in bxt_ddi_phy_calc_lane_lat_optim_mask()
581 MISSING_CASE(lane_count); in bxt_ddi_phy_calc_lane_lat_optim_mask()
660 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
673 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
726 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
752 if (crtc->config->lane_count > 2) { in chv_data_lane_soft_reset()
769 if (crtc->config->lane_count > 2) { in chv_data_lane_soft_reset()
836 if (intel_crtc->config->lane_count > 2) { in chv_phy_pre_pll_enable()
881 if (intel_crtc->config->lane_count > 2) { in chv_phy_pre_encoder_enable()
[all …]
H A Dintel_dsi.c43 8 * 100), lane_count); in txbyteclkhs()
50 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1087 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1191 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1193 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1195 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1307 unsigned int lane_count = intel_dsi->lane_count; in set_dsi_timings() local
1330 hactive = txbyteclkhs(hactive, bpp, lane_count, in set_dsi_timings()
1333 hsync = txbyteclkhs(hsync, bpp, lane_count, in set_dsi_timings()
1493 intel_dsi->lane_count, in intel_dsi_prepare()
[all …]
H A Dintel_dsi_pll.c42 int lane_count) in dsi_clk_from_pclk() argument
49 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
123 intel_dsi->lane_count); in vlv_compute_dsi_pll()
325 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); in vlv_dsi_get_pclk()
354 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); in bxt_dsi_get_pclk()
492 intel_dsi->lane_count); in gen9lp_compute_dsi_pll()
H A Dintel_dp_mst.c44 int lane_count, slots; in intel_dp_mst_compute_config() local
61 lane_count = intel_dp_max_lane_count(intel_dp); in intel_dp_mst_compute_config()
63 pipe_config->lane_count = lane_count; in intel_dp_mst_compute_config()
82 intel_link_compute_m_n(bpp, lane_count, in intel_dp_mst_compute_config()
304 pipe_config->lane_count = in intel_dp_mst_enc_get_config()
H A Dintel_dsi_vbt.c525 intel_dsi->lane_count = mipi_config->lane_cnt + 1; in intel_dsi_vbt_init()
566 computed_ddr = (pclk * bpp) / intel_dsi->lane_count; in intel_dsi_vbt_init()
589 bitrate = (pclk * bpp) / intel_dsi->lane_count; in intel_dsi_vbt_init()
607 switch (intel_dsi->lane_count) { in intel_dsi_vbt_init()
750 DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count); in intel_dsi_vbt_init()
H A Dintel_dp.c327 uint8_t lane_count) in intel_dp_link_params_valid() argument
338 if (lane_count == 0 || in intel_dp_link_params_valid()
356 } else if (lane_count > 1) { in intel_dp_get_link_train_fallback_values()
1639 int lane_count, clock; in intel_dp_compute_config() local
1754 lane_count <<= 1) { in intel_dp_compute_config()
1758 lane_count); in intel_dp_compute_config()
1785 pipe_config->lane_count = lane_count; in intel_dp_compute_config()
1848 intel_dp->lane_count = lane_count; in intel_dp_set_link_params()
1863 pipe_config->lane_count, in intel_dp_prepare()
2642 pipe_config->lane_count = in intel_dp_get_config()
[all …]
H A Dintel_dsi.h62 unsigned int lane_count; member
H A Dintel_drv.h733 uint8_t lane_count; member
957 uint8_t lane_count; member
1514 int link_rate, uint8_t lane_count,
1517 int link_rate, uint8_t lane_count);
1572 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
1574 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
H A Dintel_ddi.c1070 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); in intel_ddi_init_dp_buf_reg()
1630 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_enable_transcoder_func()
1633 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_enable_transcoder_func()
2016 width = intel_dp->lane_count; in cnl_ddi_vswing_sequence()
2195 crtc_state->lane_count, is_mst); in intel_ddi_pre_enable_dp()
2599 pipe_config->lane_count = 4; in intel_ddi_get_config()
2605 pipe_config->lane_count = in intel_ddi_get_config()
2665 pipe_config->lane_count); in intel_ddi_compute_config()
H A Dintel_hdmi.c998 pipe_config->lane_count = 4; in intel_hdmi_get_config()
1494 pipe_config->lane_count = 4; in intel_hdmi_compute_config()
H A Dintel_cdclk.c1797 crtc_state->lane_count == 4) { in intel_crtc_compute_min_cdclk()
/dragonfly/sys/dev/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_debugfs.c97 link->cur_link_settings.lane_count, in dp_link_settings_read()
104 link->verified_link_cap.lane_count, in dp_link_settings_read()
111 link->reported_link_cap.lane_count, in dp_link_settings_read()
118 link->preferred_link_setting.lane_count, in dp_link_settings_read()
227 prefer_link_settings.lane_count = param[0]; in dp_link_settings_write()
387 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
388 link->preferred_link_setting.lane_count; in dp_phy_settings_write()
395 link->cur_link_settings.lane_count; in dp_phy_settings_write()
632 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; in dp_phy_test_pattern_debugfs_write()
636 cur_link_settings.lane_count = link->cur_link_settings.lane_count; in dp_phy_test_pattern_debugfs_write()
[all …]
H A Damdgpu_dm_mst_types.c424 aconnector->dc_link->cur_link_settings.lane_count = 0; in dm_dp_destroy_mst_connector()
/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c482 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in configure_encoder()
981 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_output()
1020 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_mst_output()
1099 cntl.lanes_number = link_settings->link_settings.lane_count; in dce110_link_encoder_dp_set_lane_settings()
1104 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { in dce110_link_encoder_dp_set_lane_settings()
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_link_encoder.c449 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in configure_encoder()
930 cntl.lanes_number = link_settings->lane_count; in dcn10_link_encoder_enable_dp_output()
969 cntl.lanes_number = link_settings->lane_count; in dcn10_link_encoder_enable_dp_mst_output()
1052 cntl.lanes_number = link_settings->link_settings.lane_count; in dcn10_link_encoder_dp_set_lane_settings()
1057 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { in dcn10_link_encoder_dp_set_lane_settings()
/dragonfly/sys/dev/drm/
H A Ddrm_dp_helper.c61 int lane_count) in drm_dp_channel_eq_ok() argument
71 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
81 int lane_count) in drm_dp_clock_recovery_ok() argument
86 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
/dragonfly/sys/dev/drm/include/drm/
H A Ddrm_dp_helper.h886 int lane_count);
888 int lane_count);
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Datombios_dp.c207 int lane_count, in amdgpu_atombios_dp_get_adjust_train() argument
214 for (lane = 0; lane < lane_count; lane++) { in amdgpu_atombios_dp_get_adjust_train()
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
H A Ddce110_hw_sequencer.c697 enum dc_lane_count lane_count = in dce110_enable_stream() local
698 pipe_ctx->stream->sink->link->cur_link_settings.lane_count; in dce110_enable_stream()
725 if (lane_count != 0) in dce110_enable_stream()
726 early_control = active_total_with_borders % lane_count; in dce110_enable_stream()
729 early_control = lane_count; in dce110_enable_stream()
2459 cfg->link_settings.lane_count = in dce110_fill_display_configs()
2460 stream->sink->link->cur_link_settings.lane_count; in dce110_fill_display_configs()
/dragonfly/sys/dev/drm/radeon/
H A Datombios_dp.c257 int lane_count, in dp_get_adjust_train() argument
264 for (lane = 0; lane < lane_count; lane++) { in dp_get_adjust_train()
/dragonfly/sys/dev/drm/amd/display/dc/
H A Ddc_dp_types.h91 enum dc_lane_count lane_count; member

12