/dragonfly/sys/dev/drm/amd/powerplay/smumgr/ |
H A D | vegam_smumgr.c | 454 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in vegam_populate_smc_mvdd_table() 632 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) in vegam_get_dependency_volt_by_clk() 661 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) in vegam_get_dependency_volt_by_clk() 1092 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { in vegam_populate_mvdd_value() 1174 if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) || in vegam_populate_smc_acpi_level() 1708 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { in vegam_populate_vr_config() 1723 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in vegam_populate_vr_config()
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H A D | fiji_smumgr.c | 396 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) in fiji_get_dependency_volt_by_clk() 421 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) in fiji_get_dependency_volt_by_clk() 1292 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { in fiji_populate_mvdd_value() 1403 if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) || in fiji_populate_smc_acpi_level() 1862 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { in fiji_populate_vr_config() 1865 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in fiji_populate_vr_config()
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H A D | polaris10_smumgr.c | 383 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) in polaris10_get_dependency_volt_by_clk() 408 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) in polaris10_get_dependency_volt_by_clk() 651 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in polaris10_populate_smc_mvdd_table() 1180 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { in polaris10_populate_mvdd_value() 1257 if (!((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) || in polaris10_populate_smc_acpi_level() 1624 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { in polaris10_populate_vr_config()
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H A D | tonga_smumgr.c | 362 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in tonga_populate_smc_mvdd_table() 984 if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE) in tonga_populate_single_memory_level() 1141 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { in tonga_populate_mvdd_value() 1779 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in tonga_populate_vr_config()
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H A D | iceland_smumgr.c | 682 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) in iceland_populate_smc_mvdd_table() 1401 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { in iceland_populate_mvdd_value() 1919 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) in iceland_populate_smc_svi2_config()
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H A D | ci_smumgr.c | 910 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in ci_populate_smc_mvdd_table() 1354 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { in ci_populate_mvdd_value() 1931 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in ci_populate_vr_config()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | cypress_dpm.c | 658 if (!pi->mvdd_control) { in cypress_populate_mvdd_value() 1581 pi->mvdd_control = false; in cypress_get_mvdd_configuration() 1596 pi->mvdd_control = false; in cypress_get_mvdd_configuration() 1604 pi->mvdd_control = false; in cypress_get_mvdd_configuration() 1825 if (pi->mvdd_control) { in cypress_dpm_enable() 2074 pi->mvdd_control = in cypress_dpm_init()
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H A D | ci_dpm.h | 196 u32 mvdd_control; member
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H A D | rv770_dpm.h | 82 bool mvdd_control; member
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H A D | rv770_dpm.c | 601 if (!pi->mvdd_control) { in rv770_populate_mvdd_value() 1152 if (pi->mvdd_control) { in rv770_populate_smc_mvdd_table() 1322 pi->mvdd_control = false; in rv770_get_mvdd_configuration() 1330 pi->mvdd_control = false; in rv770_get_mvdd_configuration() 1922 if (pi->mvdd_control) { in rv770_dpm_enable() 2395 pi->mvdd_control = in rv770_dpm_init()
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H A D | ci_dpm.c | 2209 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables() 2215 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables() 2310 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_mvdd_table() 2347 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_mvdd_value() 5893 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init() 5910 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init() 5912 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
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H A D | si_dpm.c | 4002 if (pi->mvdd_control) { in si_construct_voltage_tables() 4007 pi->mvdd_control = false; in si_construct_voltage_tables() 4012 pi->mvdd_control = false; in si_construct_voltage_tables() 4135 if (pi->mvdd_control) { in si_populate_mvdd_value() 4357 if (pi->mvdd_control) in si_populate_initial_mvdd_value() 6357 if (pi->mvdd_control) in si_dpm_enable() 6996 pi->mvdd_control = in si_dpm_init()
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H A D | btc_dpm.c | 2401 if (pi->mvdd_control) { in btc_dpm_enable() 2633 pi->mvdd_control = in btc_dpm_init()
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H A D | ni_dpm.c | 1327 if (!pi->mvdd_control) { in ni_populate_mvdd_value() 4138 pi->mvdd_control = in ni_dpm_init()
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/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/ |
H A D | smu7_hwmgr.h | 229 uint32_t mvdd_control; member
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H A D | vega10_hwmgr.h | 320 uint32_t mvdd_control; member
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H A D | vega12_hwmgr.h | 324 uint32_t mvdd_control; member
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H A D | smu7_hwmgr.c | 256 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { in smu7_construct_voltage_tables() 263 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { in smu7_construct_voltage_tables() 1580 data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE; in smu7_init_dpm_defaults() 1640 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; in smu7_init_dpm_defaults() 1643 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; in smu7_init_dpm_defaults() 1660 if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE) in smu7_init_dpm_defaults()
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H A D | vega10_hwmgr.c | 818 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE; in vega10_hwmgr_backend_init() 848 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2; in vega10_hwmgr_backend_init() 1136 if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 || in vega10_construct_voltage_tables() 1137 data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) { in vega10_construct_voltage_tables()
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H A D | vega12_hwmgr.c | 389 data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE; in vega12_hwmgr_backend_init()
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | si_dpm.h | 539 bool mvdd_control; member
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H A D | si_dpm.c | 4465 if (pi->mvdd_control) { in si_construct_voltage_tables() 4470 pi->mvdd_control = false; in si_construct_voltage_tables() 4475 pi->mvdd_control = false; in si_construct_voltage_tables() 4598 if (pi->mvdd_control) { in si_populate_mvdd_value() 4822 if (pi->mvdd_control) in si_populate_initial_mvdd_value() 6790 if (pi->mvdd_control) in si_dpm_enable() 7401 pi->mvdd_control = in si_dpm_init()
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