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Searched refs:vclk (Results 1 – 25 of 46) sorted by relevance

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/dragonfly/sys/dev/drm/radeon/
H A Drs780_dpm.c570 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
587 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
727 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rs780_parse_pplib_non_clock_info()
730 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
736 rps->vclk = RS780_DEFAULT_VCLK_FREQ; in rs780_parse_pplib_non_clock_info()
944 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
993 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
H A Dtrinity_dpm.c903 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
915 if ((rps1->vclk == rps2->vclk) && in trinity_uvd_clocks_equal()
948 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
959 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1463 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && in trinity_get_uvd_clock_index()
1697 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in trinity_parse_pplib_non_clock_info()
1700 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1937 pi->sys_info.uvd_clock_table_entries[i].vclk = in trinity_parse_sys_info_table()
2023 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
2048 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
H A Dsumo_dpm.c827 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
843 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_before_set_eng_clock()
861 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_after_set_eng_clock()
1417 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in sumo_parse_pplib_non_clock_info()
1420 rps->vclk = 0; in sumo_parse_pplib_non_clock_info()
1804 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1827 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1835 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
H A Drv770_dpm.c1443 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_before_set_eng_clock()
1450 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1460 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_after_set_eng_clock()
1467 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2158 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rv7xx_parse_pplib_non_clock_info()
2161 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2166 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2167 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2444 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2488 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
H A Drv6xx_dpm.c1519 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_before_set_eng_clock()
1526 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1536 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_after_set_eng_clock()
1543 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1804 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1807 rps->vclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
H A Dradeon_uvd.c960 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
975 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers()
990 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers()
1002 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
H A Dtrinity_dpm.h69 u32 vclk; member
H A Dradeon_asic.h413 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
480 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
536 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
537 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
782 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
829 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
H A Drv770.c44 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in rv770_set_uvd_clocks() argument
51 return evergreen_set_uvd_clocks(rdev, vclk, dclk); in rv770_set_uvd_clocks()
58 if (!vclk || !dclk) { in rv770_set_uvd_clocks()
64 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in rv770_set_uvd_clocks()
H A Dni_dpm.c3513 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_before_set_eng_clock()
3521 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3531 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_after_set_eng_clock()
3539 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock()
3902 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in ni_parse_pplib_non_clock_info()
3905 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in ni_parse_pplib_non_clock_info()
3908 rps->vclk = 0; in ni_parse_pplib_non_clock_info()
4286 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_print_power_state()
4314 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_debugfs_print_current_performance_level()
H A Dkv_dpm.c832 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
837 (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk); in kv_populate_uvd_table()
842 table->entries[i].vclk, false, &dividers); in kv_populate_uvd_table()
2218 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2591 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in kv_parse_pplib_non_clock_info()
2594 rps->vclk = 0; in kv_parse_pplib_non_clock_info()
2851 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in kv_dpm_print_power_state()
H A Dradeon.h1352 u32 vclk; member
1438 u32 vclk; member
1706 unsigned vclk, unsigned dclk,
1971 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu8_hwmgr.c140 if (clock <= ptable->entries[i].vclk) in smu8_get_uvd_level()
148 if (clock >= ptable->entries[i].vclk) in smu8_get_uvd_level()
513 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; in smu8_upload_pptable_to_smu()
597 clock = table->entries[level].vclk; in smu8_init_uvd_limit()
599 clock = table->entries[table->count - 1].vclk; in smu8_init_uvd_limit()
1382 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu8_dpm_get_pp_table_entry()
1686 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; in smu8_read_sensor() local
1720 vclk = uvd_table->entries[uvd_index].vclk; in smu8_read_sensor()
1721 *((uint32_t *)value) = vclk; in smu8_read_sensor()
1848 ptable->entries[ptable->count - 1].vclk; in smu8_dpm_update_uvd_dpm()
H A Dhwmgr_ppt.h60 uint32_t vclk; /* UVD V-clock */ member
H A Dsmu10_hwmgr.h97 uint32_t vclk; member
H A Dsmu8_hwmgr.h114 uint32_t vclk; member
H A Dsmu7_hwmgr.h68 uint32_t vclk; member
H A Dvega10_hwmgr.h96 uint32_t vclk; member
H A Dvega10_hwmgr.c1362 dep_mm_table->entries[i].vclk) { in vega10_setup_default_dpm_tables()
1364 dep_mm_table->entries[i].vclk; in vega10_setup_default_dpm_tables()
2031 if (dep_table->entries[i].vclk == in vega10_populate_smc_uvd_levels()
3087 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; in vega10_get_pp_table_entry()
4419 …*equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk)… in vega10_check_states_equal()
/dragonfly/sys/dev/drm/amd/powerplay/inc/
H A Dpower_state.h176 unsigned long vclk; member
H A Dhwmgr.h105 uint32_t vclk; member
132 uint32_t vclk; member
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_dpm.h60 u32 vclk; member
148 u32 vclk; member
H A Dvi.c764 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in vi_set_uvd_clocks() argument
769 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS); in vi_set_uvd_clocks()
777 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); in vi_set_uvd_clocks()
H A Dsi_dpm.c2370 amdgpu_state->vclk && amdgpu_state->dclk) in si_should_disable_uvd_powertune()
3177 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_before_set_eng_clock()
3185 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3195 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_after_set_eng_clock()
3478 if (rps->vclk || rps->dclk) { in si_apply_state_adjust_rules()
5630 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0)) in si_is_state_ulv_compatible()
5667 if (amdgpu_state->vclk && amdgpu_state->dclk) { in si_convert_power_state_to_smc()
7113 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in si_parse_pplib_non_clock_info()
7116 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in si_parse_pplib_non_clock_info()
7119 rps->vclk = 0; in si_parse_pplib_non_clock_info()
[all …]
H A Dcik.c1328 static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in cik_set_uvd_clocks() argument
1332 r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); in cik_set_uvd_clocks()

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