Home
last modified time | relevance | path

Searched refs:PACKET3_SET_CONTEXT_REG_START (Results 1 – 19 of 19) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dsi_enums.h263 #define PACKET3_SET_CONTEXT_REG_START 0x000a000 macro
H A Dsoc15d.h291 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
H A Dnvd.h322 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
H A Dvid.h343 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
H A Dcikd.h461 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
H A Dgfx_v7_0.c2490 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_cp_gfx_start()
2498 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_cp_gfx_start()
3938 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_get_csb_buffer()
3948 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_get_csb_buffer()
H A Dsid.h1849 #define PACKET3_SET_CONTEXT_REG_START 0x000a000 macro
H A Dgfx_v11_0.c639 PACKET3_SET_CONTEXT_REG_START); in gfx_v11_0_get_csb_buffer()
649 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_get_csb_buffer()
3163 PACKET3_SET_CONTEXT_REG_START); in gfx_v11_0_cp_gfx_start()
3171 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_cp_gfx_start()
H A Dgfx_v8_0.c1235 PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_get_csb_buffer()
1246 PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_get_csb_buffer()
4175 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_cp_gfx_start()
4183 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_cp_gfx_start()
H A Dgfx_v6_0.c2025 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v6_0_cp_gfx_start()
2870 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v6_0_get_csb_buffer()
H A Dgfx_v10_0.c4096 PACKET3_SET_CONTEXT_REG_START); in gfx_v10_0_get_csb_buffer()
4106 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v10_0_get_csb_buffer()
5982 PACKET3_SET_CONTEXT_REG_START); in gfx_v10_0_cp_gfx_start()
5990 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v10_0_cp_gfx_start()
H A Dgfx_v9_0.c1462 PACKET3_SET_CONTEXT_REG_START); in gfx_v9_0_get_csb_buffer()
3064 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v9_0_cp_gfx_start()
/openbsd/sys/dev/pci/drm/radeon/
H A Devergreen_cs.c2317 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START; in evergreen_packet3_check()
2319 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) || in evergreen_packet3_check()
2628 allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START; in evergreen_packet3_check()
3503 allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START; in evergreen_vm_packet3_check()
H A Dnid.h1273 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
H A Dsid.h1786 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
H A Dcikd.h1929 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
H A Devergreend.h1669 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
H A Dsi.c5747 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in si_get_csb_buffer()
H A Dcik.c6732 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in cik_get_csb_buffer()