/dports/games/iortcw/iortcw-1.51c/MP/code/qcommon/ |
H A D | vm_powerpc_asm.c | 637 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro
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/dports/games/ioquake3/ioquake3-1.36/code/qcommon/ |
H A D | vm_powerpc_asm.c | 640 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro
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/dports/games/ioquake3-server/ioquake3-1.36/code/qcommon/ |
H A D | vm_powerpc_asm.c | 640 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro
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/dports/games/iortcw/iortcw-1.51c/SP/code/qcommon/ |
H A D | vm_powerpc_asm.c | 637 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro
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/dports/games/openarena/openarena-engine-source-0.8.8/code/qcommon/ |
H A D | vm_powerpc_asm.c | 639 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro
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/dports/games/openarena-server/openarena-engine-source-0.8.8/code/qcommon/ |
H A D | vm_powerpc_asm.c | 639 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro
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/dports/lang/smalltalk/smalltalk-3.2.5/opcode/ |
H A D | ppc-opc.c | 1043 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 1907 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 1911 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/editors/hte/ht-e9e63373148da5d7df397d8075740d8c096ecb1d/asm/ |
H A D | ppcopc.cc | 918 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 2250 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 2255 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | ppc-opc.c | 1517 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3083 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3087 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/ |
H A D | ppc-opc.c | 1532 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3137 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3141 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | ppc-opc.c | 1517 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3083 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3087 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/devel/djgpp-binutils/binutils-2.17/opcodes/ |
H A D | ppc-opc.c | 1578 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3187 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3191 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/emulators/qemu/qemu-6.2.0/disas/ |
H A D | ppc.c | 1690 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3337 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3341 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/emulators/qemu42/qemu-4.2.1/disas/ |
H A D | ppc.c | 1690 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3337 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3341 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/ |
H A D | ppc-dis.c | 1689 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3326 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3330 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/emulators/qemu5/qemu-5.2.0/disas/ |
H A D | ppc.c | 1690 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3337 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3341 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/emulators/qemu60/qemu-6.0.0/disas/ |
H A D | ppc.c | 1690 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3337 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3341 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/ |
H A D | ppc.c | 1690 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3334 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3338 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/ppc/gnu/ |
H A D | ppc-opc.c | 1528 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3304 {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, {RA, RS, MB}}, 3308 {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, {RA, RS, MB}},
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/dports/emulators/qemu-utils/qemu-4.2.1/disas/ |
H A D | ppc.c | 1690 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3337 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3341 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/ |
H A D | ppc.c | 1690 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3337 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3341 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/ |
H A D | ppc.c | 1690 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3337 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3341 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/ |
H A D | ppc.c | 1690 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3337 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3341 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
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/dports/devel/avr-gdb/gdb-7.3.1/opcodes/ |
H A D | ppc-opc.c | 1565 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 3368 {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}}, 3372 {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
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/dports/devel/gdb761/gdb-7.6.1/opcodes/ |
H A D | ppc-opc.c | 2257 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) macro 4161 {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}}, 4165 {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}},
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