/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/ppc/libps/ |
H A D | libps.c | 57 { ps_neg, "ps_neg", OPLC (4, 40, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Negate"}, 59 { ps_mr, "ps_mr", OPLC (4, 72, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Move Register"}, 61 …{ ps_nabs, "ps_nabs", OPLC (4, 136, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Negative Absolut… 63 { ps_abs, "ps_abs", OPLC (4, 264, 0), OPL_MASK, { OP_FD, OP_FB}, "Paired Single Absolute Value"}, 80 …{ ps_cmpo0, "ps_cmpo0", OPL (4, 32), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare O… 82 …{ ps_cmpo1, "ps_cmpo1", OPL (4, 96), OPL_MASK, { OP_crfD, OP_FA, OP_FB}, "Paired Singles Compare O… 84 …{ ps_merge00, "ps_merge00", OPLC (4, 528, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MER… 86 …{ ps_merge01, "ps_merge01", OPLC (4, 560, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MER… 88 …{ ps_merge10, "ps_merge10", OPLC (4, 592, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MER… 90 …{ ps_merge11, "ps_merge11", OPLC (4, 624, 0), OPL_MASK, { OP_FD, OP_FA, OP_FB}, "Paired Single MER… [all …]
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H A D | libps_internal.h | 27 #define OPL_MASK OPLC(0x3f, 0x3ff, 1) macro
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/dports/games/iortcw/iortcw-1.51c/MP/code/qcommon/ |
H A D | vm_powerpc_asm.c | 553 #define OPL_MASK OPL (0x3f,1) macro 927 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 928 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
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/dports/games/ioquake3/ioquake3-1.36/code/qcommon/ |
H A D | vm_powerpc_asm.c | 556 #define OPL_MASK OPL (0x3f,1) macro 930 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 931 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
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/dports/games/ioquake3-server/ioquake3-1.36/code/qcommon/ |
H A D | vm_powerpc_asm.c | 556 #define OPL_MASK OPL (0x3f,1) macro 930 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 931 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
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/dports/games/iortcw/iortcw-1.51c/SP/code/qcommon/ |
H A D | vm_powerpc_asm.c | 553 #define OPL_MASK OPL (0x3f,1) macro 927 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 928 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
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/dports/games/openarena/openarena-engine-source-0.8.8/code/qcommon/ |
H A D | vm_powerpc_asm.c | 555 #define OPL_MASK OPL (0x3f,1) macro 929 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 930 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
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/dports/games/openarena-server/openarena-engine-source-0.8.8/code/qcommon/ |
H A D | vm_powerpc_asm.c | 555 #define OPL_MASK OPL (0x3f,1) macro 929 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 930 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
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/dports/lang/smalltalk/smalltalk-3.2.5/opcode/ |
H A D | ppc-opc.c | 984 #define OPL_MASK OPL (0x3f,1) macro 1311 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 1312 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 1316 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 1317 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/editors/hte/ht-e9e63373148da5d7df397d8075740d8c096ecb1d/asm/ |
H A D | ppcopc.cc | 837 #define OPL_MASK OPL (0x3f,1) macro 1559 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 1560 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 1563 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 1564 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | ppc-opc.c | 1436 #define OPL_MASK OPL (0x3f,1) macro 2360 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2361 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2365 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2366 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/ |
H A D | ppc-opc.c | 1451 #define OPL_MASK OPL (0x3f,1) macro 2414 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2415 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2419 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2420 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
H A D | ppc-opc.c | 1436 #define OPL_MASK OPL (0x3f,1) macro 2360 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2361 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2365 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2366 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/devel/djgpp-binutils/binutils-2.17/opcodes/ |
H A D | ppc-opc.c | 1497 #define OPL_MASK OPL (0x3f,1) macro 2462 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2463 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2467 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2468 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/emulators/qemu/qemu-6.2.0/disas/ |
H A D | ppc.c | 1606 #define OPL_MASK OPL (0x3f,1) macro 2605 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2606 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2610 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2611 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/emulators/qemu42/qemu-4.2.1/disas/ |
H A D | ppc.c | 1606 #define OPL_MASK OPL (0x3f,1) macro 2605 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2606 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2610 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2611 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/ |
H A D | ppc-dis.c | 1605 #define OPL_MASK OPL (0x3f,1) macro 2594 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2595 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2599 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2600 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/emulators/qemu5/qemu-5.2.0/disas/ |
H A D | ppc.c | 1606 #define OPL_MASK OPL (0x3f,1) macro 2605 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2606 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2610 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2611 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/emulators/qemu60/qemu-6.0.0/disas/ |
H A D | ppc.c | 1606 #define OPL_MASK OPL (0x3f,1) macro 2605 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2606 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2610 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2611 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/ |
H A D | ppc.c | 1606 #define OPL_MASK OPL (0x3f,1) macro 2602 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2603 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2607 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2608 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/ppc/gnu/ |
H A D | ppc-opc.c | 1444 #define OPL_MASK OPL (0x3f,1) macro 2552 {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, {OBF, RA, UI}}, 2553 {"cmpldi", OPL(10,1), OPL_MASK, PPC64, {OBF, RA, UI}}, 2557 {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, {OBF, RA, SI}}, 2558 {"cmpdi", OPL(11,1), OPL_MASK, PPC64, {OBF, RA, SI}},
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/dports/emulators/qemu-utils/qemu-4.2.1/disas/ |
H A D | ppc.c | 1606 #define OPL_MASK OPL (0x3f,1) macro 2605 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2606 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2610 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2611 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/ |
H A D | ppc.c | 1606 #define OPL_MASK OPL (0x3f,1) macro 2605 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2606 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2610 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2611 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/ |
H A D | ppc.c | 1606 #define OPL_MASK OPL (0x3f,1) macro 2605 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2606 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2610 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2611 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/ |
H A D | ppc.c | 1606 #define OPL_MASK OPL (0x3f,1) macro 2605 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2606 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2610 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2611 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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