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Searched refs:TOLLE (Results 1 – 25 of 36) sorted by relevance

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/dports/devel/vasm/vasm/cpus/ppc/
H A Dcpu.h248 #define TOLLE (0x6) macro
H A Dopcodes.h6 "tdllei", { RA, SI } ,{PPC64, OPTO(2,TOLLE)},
27 "twllei", { RA, SI } ,{PPCCOM, OPTO(3,TOLLE)},
28 "tllei", { RA, SI } ,{PWRCOM, OPTO(3,TOLLE)},
1288 "twlle", { RA, RB } ,{PPCCOM, XTO(31,4,TOLLE)},
1289 "tlle", { RA, RB } ,{PWRCOM, XTO(31,4,TOLLE)},
1406 "tdlle", { RA, RB } ,{PPC64, XTO(31,68,TOLLE)},
/dports/lang/smalltalk/smalltalk-3.2.5/opcode/
H A Dppc-opc.c1208 #define TOLLE (0x6) macro
1261 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1282 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1283 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1983 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
1984 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
2093 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/games/iortcw/iortcw-1.51c/MP/code/qcommon/
H A Dvm_powerpc_asm.c887 #define TOLLE (0x6) macro
/dports/games/ioquake3/ioquake3-1.36/code/qcommon/
H A Dvm_powerpc_asm.c890 #define TOLLE (0x6) macro
/dports/games/ioquake3-server/ioquake3-1.36/code/qcommon/
H A Dvm_powerpc_asm.c890 #define TOLLE (0x6) macro
/dports/games/iortcw/iortcw-1.51c/SP/code/qcommon/
H A Dvm_powerpc_asm.c887 #define TOLLE (0x6) macro
/dports/games/openarena/openarena-engine-source-0.8.8/code/qcommon/
H A Dvm_powerpc_asm.c889 #define TOLLE (0x6) macro
/dports/games/openarena-server/openarena-engine-source-0.8.8/code/qcommon/
H A Dvm_powerpc_asm.c889 #define TOLLE (0x6) macro
/dports/editors/hte/ht-e9e63373148da5d7df397d8075740d8c096ecb1d/asm/
H A Dppcopc.cc1192 #define TOLLE (0x6) macro
1270 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1291 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1292 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
2311 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
2394 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dppc-opc.c1742 #define TOLLE (0x6) macro
1815 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1836 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1837 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
3164 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3165 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3291 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/
H A Dppc-opc.c1761 #define TOLLE (0x6) macro
1834 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1855 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1856 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
3218 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3219 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3346 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dppc-opc.c1742 #define TOLLE (0x6) macro
1815 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1836 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1837 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
3164 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3165 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3291 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/
H A Dppc-opc.c1807 #define TOLLE (0x6) macro
1882 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1903 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1904 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
3268 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3269 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3396 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/emulators/qemu/qemu-6.2.0/disas/
H A Dppc.c1941 #define TOLLE (0x6) macro
2021 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2042 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2043 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
3418 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3419 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3546 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/emulators/qemu42/qemu-4.2.1/disas/
H A Dppc.c1941 #define TOLLE (0x6) macro
2021 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2042 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2043 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
3418 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3419 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3546 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/
H A Dppc-dis.c1937 #define TOLLE (0x6) macro
2014 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2035 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2036 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
3407 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3408 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3535 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/emulators/qemu5/qemu-5.2.0/disas/
H A Dppc.c1941 #define TOLLE (0x6) macro
2021 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2042 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2043 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
3418 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3419 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3546 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/emulators/qemu60/qemu-6.0.0/disas/
H A Dppc.c1941 #define TOLLE (0x6) macro
2021 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2042 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2043 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
3418 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3419 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3546 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/
H A Dppc.c1938 #define TOLLE (0x6) macro
2018 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2039 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2040 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
3415 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3416 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3543 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/ppc/gnu/
H A Dppc-opc.c1819 #define TOLLE (0x6) macro
1904 {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, {RA, SI}},
1925 {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, {RA, SI}},
1926 {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, {RA, SI}},
3384 {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, {RA, RB}},
3385 {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, {RA, RB}},
3517 {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, {RA, RB}},
/dports/emulators/qemu-utils/qemu-4.2.1/disas/
H A Dppc.c1941 #define TOLLE (0x6) macro
2021 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2042 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2043 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
3418 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3419 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3546 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/
H A Dppc.c1941 #define TOLLE (0x6) macro
2021 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2042 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2043 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
3418 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3419 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3546 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/
H A Dppc.c1941 #define TOLLE (0x6) macro
2021 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2042 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2043 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
3418 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3419 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3546 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/
H A Dppc.c1941 #define TOLLE (0x6) macro
2021 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2042 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2043 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
3418 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3419 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3546 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },

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