| /dragonfly/sys/dev/drm/amd/include/ |
| H A D | v9_structs.h | 70 uint32_t reserved_42;
71 uint32_t reserved_43;
72 uint32_t reserved_44;
73 uint32_t reserved_45;
74 uint32_t reserved_46;
75 uint32_t reserved_47;
76 uint32_t reserved_48;
77 uint32_t reserved_49;
78 uint32_t reserved_50;
79 uint32_t reserved_51;
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| H A D | vi_structs.h | 50 uint32_t reserved_22;
51 uint32_t reserved_23;
52 uint32_t reserved_24;
53 uint32_t reserved_25;
54 uint32_t reserved_26;
55 uint32_t reserved_27;
56 uint32_t reserved_28;
57 uint32_t reserved_29;
58 uint32_t reserved_30;
161 uint32_t header;
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| H A D | cik_structs.h | 28 uint32_t header;
30 uint32_t compute_dim_x;
31 uint32_t compute_dim_y;
32 uint32_t compute_dim_z;
49 uint32_t compute_vmid;
82 uint32_t cp_hqd_vmid;
124 uint32_t reserved_96;
125 uint32_t reserved_97;
126 uint32_t reserved_98;
127 uint32_t reserved_99;
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| /dragonfly/sys/dev/netif/oce/ |
| H A D | oce_hw.h | 220 uint32_t dw0;
249 uint32_t lo;
251 uint32_t hi;
257 uint32_t dw0;
281 uint32_t dw0;
297 uint32_t dw0;
321 uint32_t dw0;
376 uint32_t dw0;
404 uint32_t dw0;
431 uint32_t dw0;
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| /dragonfly/sys/dev/drm/amd/display/include/ |
| H A D | grph_object_ctrl_defs.h | 93 uint32_t i2c_line;
104 uint32_t acpi_device;
121 uint32_t RGB888:1;
123 uint32_t SPATIAL:1;
124 uint32_t TEMPORAL:1;
151 uint32_t ss_id;
153 uint32_t drr_enabled;
186 uint32_t step;
187 uint32_t delay;
224 uint32_t gpio_id;
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| H A D | bios_parser_types.h | 151 uint32_t pixel_clock;
152 uint32_t lane_select;
162 uint32_t h_total;
166 uint32_t h_sync_start;
167 uint32_t h_sync_width;
170 uint32_t v_total;
194 uint32_t pixel_clock;
278 uint32_t DS_TYPE:1;
283 uint32_t percentage;
288 uint32_t step;
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| /dragonfly/sys/dev/drm/amd/display/dc/ |
| H A D | dc_helper.c | 33 uint32_t addr, uint32_t reg_val, int n, in generic_reg_update_ex()
255 uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value, in generic_reg_wait()
304 uint32_t addr_index, uint32_t addr_data,
305 uint32_t index, uint32_t data);
307 uint32_t addr_index, uint32_t addr_data, in generic_write_indirect_reg()
308 uint32_t index, uint32_t data) in generic_write_indirect_reg()
315 uint32_t addr_index, uint32_t addr_data,
318 uint32_t addr_index, uint32_t addr_data, in generic_read_indirect_reg()
330 uint32_t addr_index, uint32_t addr_data,
331 uint32_t index, uint32_t reg_val, int n,
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| /dragonfly/sys/netproto/802_11/ |
| H A D | ieee80211_ioctl.h | 42 uint32_t ns_rx_data; /* rx data frames */
59 uint32_t ns_rx_action; /* rx action */
65 uint32_t ns_tx_data; /* tx data frames */
87 uint32_t ns_spare[8];
106 uint32_t is_rx_ctl; /* rx ctrl frames */
252 uint32_t is_spare[5];
353 uint32_t imr_metric;
354 uint32_t imr_lifetime;
355 uint32_t imr_lastmseq;
426 uint32_t isi_flags; /* channel flags */
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| /dragonfly/sys/vfs/fuse/ |
| H A D | fuse_abi.h | 183 uint32_t mode;
185 uint32_t uid;
186 uint32_t gid;
187 uint32_t rdev;
208 uint32_t type;
504 uint32_t uid;
505 uint32_t gid;
674 uint32_t cmd;
717 uint32_t len;
721 uint32_t uid;
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| /dragonfly/sys/bus/u4b/net/ |
| H A D | if_urndisreg.h | 126 uint32_t rm_len;
143 uint32_t rm_len;
144 uint32_t rm_rid;
154 uint32_t rm_len;
155 uint32_t rm_rid;
163 uint32_t rm_len;
164 uint32_t rm_rid;
182 uint32_t rm_len;
183 uint32_t rm_rid;
192 uint32_t rm_len;
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| /dragonfly/sys/dev/drm/amd/powerplay/hwmgr/ |
| H A D | smu8_hwmgr.h | 114 uint32_t vclk;
115 uint32_t dclk;
134 uint32_t vce : 1;
135 uint32_t uvd : 1;
136 uint32_t acp : 1;
139 uint32_t u32All;
145 uint32_t level;
147 uint32_t evclk;
148 uint32_t ecclk;
149 uint32_t samclk;
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| H A D | smu7_hwmgr.h | 68 uint32_t vclk;
69 uint32_t dclk;
73 uint32_t evclk;
74 uint32_t ecclk;
90 uint32_t value;
91 uint32_t param1;
99 uint32_t count;
119 uint32_t vDLL_CNTL;
177 uint32_t count;
187 uint32_t min_vddc;
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| H A D | smu10_hwmgr.h | 97 uint32_t vclk;
98 uint32_t dclk;
129 uint32_t level;
131 uint32_t evclk;
132 uint32_t ecclk;
133 uint32_t samclk;
134 uint32_t acpclk;
183 uint32_t count;
188 uint32_t clk;
189 uint32_t vol;
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| H A D | vega10_hwmgr.h | 96 uint32_t vclk;
97 uint32_t dclk;
101 uint32_t evclk;
102 uint32_t ecclk;
117 uint32_t value;
118 uint32_t param1;
134 uint32_t count;
215 uint32_t latency;
219 uint32_t count;
284 uint32_t count;
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| H A D | vega12_hwmgr.h | 91 uint32_t value;
92 uint32_t param1;
108 uint32_t count;
114 uint32_t count;
170 uint32_t eclock;
207 uint32_t latency;
211 uint32_t count;
283 uint32_t count;
308 uint32_t ACMax;
309 uint32_t ACMin;
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| /dragonfly/sys/dev/disk/nvme/ |
| H A D | nvme_chipset.h | 353 uint32_t dw2;
354 uint32_t dw3;
599 uint32_t dw0;
600 uint32_t dw1;
635 uint32_t dw1;
705 uint32_t dw0;
706 uint32_t dw1;
747 uint32_t dw0;
748 uint32_t dw1;
775 uint32_t dw0;
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | amdgpu_ucode.h | 33 uint32_t ucode_version;
49 uint32_t ucode_start_addr;
56 uint32_t sos_offset_bytes;
57 uint32_t sos_size_bytes;
131 uint32_t digest_size;
136 uint32_t gc_num_se;
140 uint32_t gc_num_tccs;
141 uint32_t gc_num_gprs;
147 uint32_t gc_wave_size;
150 uint32_t gc_lds_size;
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| H A D | psp_gfx_if.h | 64 volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */
69 volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */
101 uint32_t app_len; /* length of the TA binary in bytes */
200 uint32_t fw_size; /* FW buffer size in bytes */
233 uint32_t status; /* +0 status of command execution */
238 uint32_t reserved[4];
250 uint32_t cmd_id; /* +8 command ID */
256 uint32_t resp_offset; /* +20 offset within response buffer */
281 uint32_t cmd_buf_size; /* +8 command buffer size in bytes */
284 uint32_t fence_value; /* +20 Fence value */
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| /dragonfly/sys/dev/drm/amd/display/dc/inc/ |
| H A D | clock_source.h | 38 uint32_t freq_range_khz;
45 uint32_t feedback_amount;
46 uint32_t nfrac_amount;
47 uint32_t ds_frac_size;
48 uint32_t ds_frac_amount;
57 uint32_t ENABLE_SS:1;
110 uint32_t vco_freq;
116 uint32_t ss_percentage;
142 uint32_t ref_freq_khz;
148 uint32_t max_vco_khz;
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| /dragonfly/sys/dev/virtual/vmware/vmxnet3/ |
| H A D | if_vmxreg.h | 94 uint32_t len:14;
96 uint32_t pad1:1;
98 uint32_t pad2:1;
124 uint32_t gen:1;
134 uint32_t gen:1;
162 uint32_t udp:1;
163 uint32_t tcp:1;
170 uint32_t gen:1;
226 uint32_t pad1;
238 uint32_t mtu;
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| /dragonfly/sys/dev/drm/amd/powerplay/inc/ |
| H A D | smu72_discrete.h | 75 uint32_t Flags;
100 uint32_t Reserved;
107 uint32_t MinMvdd;
136 uint32_t DllCntl;
137 uint32_t MpllSs1;
138 uint32_t MpllSs2;
185 uint32_t Frequency;
526 uint32_t IddcHyst;
537 uint32_t Limit;
538 uint32_t Hyst;
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| H A D | smu71_discrete.h | 49 uint32_t MinVddc;
78 uint32_t Flags;
79 uint32_t MinVddc;
112 uint32_t MinVddc;
115 uint32_t MinMvdd;
144 uint32_t DllCntl;
145 uint32_t MpllSs1;
146 uint32_t MpllSs2;
202 uint32_t Frequency;
594 uint32_t filler[4];
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| H A D | smu73_discrete.h | 47 uint32_t MinVoltage;
58 uint32_t CcPwrDynRm;
73 uint32_t Flags;
98 uint32_t Reserved;
523 uint32_t IddcHyst;
534 uint32_t Limit;
535 uint32_t Hyst;
582 uint32_t b;
717 uint32_t spare[4];
755 uint32_t Fps_acc;
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| H A D | smu7_discrete.h | 105 uint32_t Flags;
106 uint32_t MinVddc;
136 uint32_t Flags;
137 uint32_t MinVddc;
170 uint32_t MinVddc;
173 uint32_t MinMvdd;
202 uint32_t DllCntl;
203 uint32_t MpllSs1;
215 uint32_t DownT;
216 uint32_t UpT;
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| H A D | smu74_discrete.h | 90 uint32_t CcPwrDynRm;
106 uint32_t Flags;
135 uint32_t MinMvdd;
196 uint32_t Frequency;
228 uint32_t b;
515 uint32_t IddcLimit;
516 uint32_t IddcHyst;
527 uint32_t Limit;
528 uint32_t Hyst;
685 uint32_t spare[4];
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